#ifndef GEN_EU_ISA_XML
#define GEN_EU_ISA_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git

Copyright (C) 2014-2015 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


enum gen_eu_opcode {
    GEN6_OPCODE_ILLEGAL					      = 0x0,
    GEN6_OPCODE_MOV					      = 0x1,
    GEN6_OPCODE_SEL					      = 0x2,
    GEN6_OPCODE_MOVI					      = 0x3,
    GEN6_OPCODE_NOT					      = 0x4,
    GEN6_OPCODE_AND					      = 0x5,
    GEN6_OPCODE_OR					      = 0x6,
    GEN6_OPCODE_XOR					      = 0x7,
    GEN6_OPCODE_SHR					      = 0x8,
    GEN6_OPCODE_SHL					      = 0x9,
    GEN6_OPCODE_DIM					      = 0xa,
    GEN6_OPCODE_ASR					      = 0xc,
    GEN6_OPCODE_CMP					      = 0x10,
    GEN6_OPCODE_CMPN					      = 0x11,
    GEN7_OPCODE_CSEL					      = 0x12,
    GEN7_OPCODE_F32TO16					      = 0x13,
    GEN7_OPCODE_F16TO32					      = 0x14,
    GEN7_OPCODE_BFREV					      = 0x17,
    GEN7_OPCODE_BFE					      = 0x18,
    GEN7_OPCODE_BFI1					      = 0x19,
    GEN7_OPCODE_BFI2					      = 0x1a,
    GEN6_OPCODE_JMPI					      = 0x20,
    GEN7_OPCODE_BRD					      = 0x21,
    GEN6_OPCODE_IF					      = 0x22,
    GEN7_OPCODE_BRC					      = 0x23,
    GEN6_OPCODE_ELSE					      = 0x24,
    GEN6_OPCODE_ENDIF					      = 0x25,
    GEN6_OPCODE_CASE					      = 0x26,
    GEN6_OPCODE_WHILE					      = 0x27,
    GEN6_OPCODE_BREAK					      = 0x28,
    GEN6_OPCODE_CONT					      = 0x29,
    GEN6_OPCODE_HALT					      = 0x2a,
    GEN75_OPCODE_CALLA					      = 0x2b,
    GEN6_OPCODE_CALL					      = 0x2c,
    GEN6_OPCODE_RETURN					      = 0x2d,
    GEN8_OPCODE_GOTO					      = 0x2e,
    GEN6_OPCODE_WAIT					      = 0x30,
    GEN6_OPCODE_SEND					      = 0x31,
    GEN6_OPCODE_SENDC					      = 0x32,
    GEN6_OPCODE_MATH					      = 0x38,
    GEN6_OPCODE_ADD					      = 0x40,
    GEN6_OPCODE_MUL					      = 0x41,
    GEN6_OPCODE_AVG					      = 0x42,
    GEN6_OPCODE_FRC					      = 0x43,
    GEN6_OPCODE_RNDU					      = 0x44,
    GEN6_OPCODE_RNDD					      = 0x45,
    GEN6_OPCODE_RNDE					      = 0x46,
    GEN6_OPCODE_RNDZ					      = 0x47,
    GEN6_OPCODE_MAC					      = 0x48,
    GEN6_OPCODE_MACH					      = 0x49,
    GEN6_OPCODE_LZD					      = 0x4a,
    GEN7_OPCODE_FBH					      = 0x4b,
    GEN7_OPCODE_FBL					      = 0x4c,
    GEN7_OPCODE_CBIT					      = 0x4d,
    GEN7_OPCODE_ADDC					      = 0x4e,
    GEN7_OPCODE_SUBB					      = 0x4f,
    GEN6_OPCODE_SAD2					      = 0x50,
    GEN6_OPCODE_SADA2					      = 0x51,
    GEN6_OPCODE_DP4					      = 0x54,
    GEN6_OPCODE_DPH					      = 0x55,
    GEN6_OPCODE_DP3					      = 0x56,
    GEN6_OPCODE_DP2					      = 0x57,
    GEN6_OPCODE_LINE					      = 0x59,
    GEN6_OPCODE_PLN					      = 0x5a,
    GEN6_OPCODE_MAD					      = 0x5b,
    GEN6_OPCODE_LRP					      = 0x5c,
    GEN6_OPCODE_NOP					      = 0x7e,
};

enum gen_eu_access_mode {
    GEN6_ALIGN_1					      = 0x0,
    GEN6_ALIGN_16					      = 0x1,
};

enum gen_eu_mask_control {
    GEN6_MASKCTRL_NORMAL				      = 0x0,
    GEN6_MASKCTRL_NOMASK				      = 0x1,
};

enum gen_eu_dependency_control {
    GEN6_DEPCTRL_NORMAL					      = 0x0,
    GEN6_DEPCTRL_NODDCLR				      = 0x1,
    GEN6_DEPCTRL_NODDCHK				      = 0x2,
    GEN6_DEPCTRL_NEITHER				      = 0x3,
};

enum gen_eu_quarter_control {
    GEN6_QTRCTRL_1Q					      = 0x0,
    GEN6_QTRCTRL_2Q					      = 0x1,
    GEN6_QTRCTRL_3Q					      = 0x2,
    GEN6_QTRCTRL_4Q					      = 0x3,
    GEN6_QTRCTRL_1H					      = 0x0,
    GEN6_QTRCTRL_2H					      = 0x2,
};

enum gen_eu_thread_control {
    GEN6_THREADCTRL_NORMAL				      = 0x0,
    GEN6_THREADCTRL_ATOMIC				      = 0x1,
    GEN6_THREADCTRL_SWITCH				      = 0x2,
};

enum gen_eu_predicate_control {
    GEN6_PREDCTRL_NONE					      = 0x0,
    GEN6_PREDCTRL_NORMAL				      = 0x1,
    GEN6_PREDCTRL_ANYV					      = 0x2,
    GEN6_PREDCTRL_ALLV					      = 0x3,
    GEN6_PREDCTRL_ANY2H					      = 0x4,
    GEN6_PREDCTRL_ALL2H					      = 0x5,
    GEN6_PREDCTRL_X					      = 0x2,
    GEN6_PREDCTRL_Y					      = 0x3,
    GEN6_PREDCTRL_Z					      = 0x4,
    GEN6_PREDCTRL_W					      = 0x5,
    GEN6_PREDCTRL_ANY4H					      = 0x6,
    GEN6_PREDCTRL_ALL4H					      = 0x7,
    GEN6_PREDCTRL_ANY8H					      = 0x8,
    GEN6_PREDCTRL_ALL8H					      = 0x9,
    GEN6_PREDCTRL_ANY16H				      = 0xa,
    GEN6_PREDCTRL_ALL16H				      = 0xb,
    GEN7_PREDCTRL_ANY32H				      = 0xc,
    GEN7_PREDCTRL_ALL32H				      = 0xd,
};

enum gen_eu_exec_size {
    GEN6_EXECSIZE_1					      = 0x0,
    GEN6_EXECSIZE_2					      = 0x1,
    GEN6_EXECSIZE_4					      = 0x2,
    GEN6_EXECSIZE_8					      = 0x3,
    GEN6_EXECSIZE_16					      = 0x4,
    GEN6_EXECSIZE_32					      = 0x5,
};

enum gen_eu_condition_modifier {
    GEN6_COND_NONE					      = 0x0,
    GEN6_COND_Z						      = 0x1,
    GEN6_COND_NZ					      = 0x2,
    GEN6_COND_G						      = 0x3,
    GEN6_COND_GE					      = 0x4,
    GEN6_COND_L						      = 0x5,
    GEN6_COND_LE					      = 0x6,
    GEN6_COND_O						      = 0x8,
    GEN6_COND_U						      = 0x9,
};

enum gen_eu_math_function_control {
    GEN6_MATH_INV					      = 0x1,
    GEN6_MATH_LOG					      = 0x2,
    GEN6_MATH_EXP					      = 0x3,
    GEN6_MATH_SQRT					      = 0x4,
    GEN6_MATH_RSQ					      = 0x5,
    GEN6_MATH_SIN					      = 0x6,
    GEN6_MATH_COS					      = 0x7,
    GEN6_MATH_FDIV					      = 0x9,
    GEN6_MATH_POW					      = 0xa,
    GEN6_MATH_INT_DIV					      = 0xb,
    GEN6_MATH_INT_DIV_QUOTIENT				      = 0xc,
    GEN6_MATH_INT_DIV_REMAINDER				      = 0xd,
    GEN8_MATH_INVM					      = 0xe,
    GEN8_MATH_RSQRTM					      = 0xf,
};

enum gen_eu_shared_function_id {
    GEN6_SFID_NULL					      = 0x0,
    GEN6_SFID_SAMPLER					      = 0x2,
    GEN6_SFID_GATEWAY					      = 0x3,
    GEN6_SFID_DP_SAMPLER				      = 0x4,
    GEN6_SFID_DP_RC					      = 0x5,
    GEN6_SFID_URB					      = 0x6,
    GEN6_SFID_SPAWNER					      = 0x7,
    GEN6_SFID_VME					      = 0x8,
    GEN6_SFID_DP_CC					      = 0x9,
    GEN7_SFID_DP_DC0					      = 0xa,
    GEN7_SFID_PI					      = 0xb,
    GEN75_SFID_DP_DC1					      = 0xc,
};

enum gen_eu_reg_file {
    GEN6_FILE_ARF					      = 0x0,
    GEN6_FILE_GRF					      = 0x1,
    GEN6_FILE_MRF					      = 0x2,
    GEN6_FILE_IMM					      = 0x3,
};

enum gen_eu_reg_type {
    GEN6_TYPE_UD					      = 0x0,
    GEN6_TYPE_D						      = 0x1,
    GEN6_TYPE_UW					      = 0x2,
    GEN6_TYPE_W						      = 0x3,
    GEN6_TYPE_UB					      = 0x4,
    GEN6_TYPE_B						      = 0x5,
    GEN7_TYPE_DF					      = 0x6,
    GEN6_TYPE_F						      = 0x7,
    GEN8_TYPE_UQ					      = 0x8,
    GEN8_TYPE_Q						      = 0x9,
    GEN8_TYPE_HF					      = 0xa,
    GEN6_TYPE_UV_IMM					      = 0x4,
    GEN6_TYPE_VF_IMM					      = 0x5,
    GEN6_TYPE_V_IMM					      = 0x6,
    GEN8_TYPE_DF_IMM					      = 0xa,
    GEN8_TYPE_HF_IMM					      = 0xb,
    GEN7_TYPE_F_3SRC					      = 0x0,
    GEN7_TYPE_D_3SRC					      = 0x1,
    GEN7_TYPE_UD_3SRC					      = 0x2,
    GEN7_TYPE_DF_3SRC					      = 0x3,
};

enum gen_eu_vertical_stride {
    GEN6_VERTSTRIDE_0					      = 0x0,
    GEN6_VERTSTRIDE_1					      = 0x1,
    GEN6_VERTSTRIDE_2					      = 0x2,
    GEN6_VERTSTRIDE_4					      = 0x3,
    GEN6_VERTSTRIDE_8					      = 0x4,
    GEN6_VERTSTRIDE_16					      = 0x5,
    GEN6_VERTSTRIDE_32					      = 0x6,
    GEN6_VERTSTRIDE_VXH					      = 0xf,
};

enum gen_eu_width {
    GEN6_WIDTH_1					      = 0x0,
    GEN6_WIDTH_2					      = 0x1,
    GEN6_WIDTH_4					      = 0x2,
    GEN6_WIDTH_8					      = 0x3,
    GEN6_WIDTH_16					      = 0x4,
};

enum gen_eu_horizontal_stride {
    GEN6_HORZSTRIDE_0					      = 0x0,
    GEN6_HORZSTRIDE_1					      = 0x1,
    GEN6_HORZSTRIDE_2					      = 0x2,
    GEN6_HORZSTRIDE_4					      = 0x3,
};

enum gen_eu_addressing_mode {
    GEN6_ADDRMODE_DIRECT				      = 0x0,
    GEN6_ADDRMODE_INDIRECT				      = 0x1,
};

enum gen_eu_swizzle {
    GEN6_SWIZZLE_X					      = 0x0,
    GEN6_SWIZZLE_Y					      = 0x1,
    GEN6_SWIZZLE_Z					      = 0x2,
    GEN6_SWIZZLE_W					      = 0x3,
};

enum gen_eu_arf_reg {
    GEN6_ARF_NULL					      = 0x0,
    GEN6_ARF_A0						      = 0x10,
    GEN6_ARF_ACC0					      = 0x20,
    GEN6_ARF_F0						      = 0x30,
    GEN6_ARF_SR0					      = 0x70,
    GEN6_ARF_CR0					      = 0x80,
    GEN6_ARF_N0						      = 0x90,
    GEN6_ARF_IP						      = 0xa0,
    GEN6_ARF_TDR					      = 0xb0,
    GEN7_ARF_TM0					      = 0xc0,
};

#define GEN6_INST_SATURATE					(0x1 << 31)
#define GEN6_INST_DEBUGCTRL					(0x1 << 30)
#define GEN6_INST_CMPTCTRL					(0x1 << 29)
#define GEN8_INST_BRANCHCTRL					(0x1 << 28)
#define GEN6_INST_ACCWRCTRL					(0x1 << 28)
#define GEN6_INST_CONDMODIFIER__MASK				0x0f000000
#define GEN6_INST_CONDMODIFIER__SHIFT				24
#define GEN6_INST_SFID__MASK					0x0f000000
#define GEN6_INST_SFID__SHIFT					24
#define GEN6_INST_FC__MASK					0x0f000000
#define GEN6_INST_FC__SHIFT					24
#define GEN6_INST_EXECSIZE__MASK				0x00e00000
#define GEN6_INST_EXECSIZE__SHIFT				21
#define GEN6_INST_PREDINV					(0x1 << 20)
#define GEN6_INST_PREDCTRL__MASK				0x000f0000
#define GEN6_INST_PREDCTRL__SHIFT				16
#define GEN6_INST_THREADCTRL__MASK				0x0000c000
#define GEN6_INST_THREADCTRL__SHIFT				14
#define GEN6_INST_QTRCTRL__MASK					0x00003000
#define GEN6_INST_QTRCTRL__SHIFT				12
#define GEN6_INST_DEPCTRL__MASK					0x00000c00
#define GEN6_INST_DEPCTRL__SHIFT				10
#define GEN6_INST_MASKCTRL__MASK				0x00000200
#define GEN6_INST_MASKCTRL__SHIFT				9
#define GEN8_INST_NIBCTRL					(0x1 << 11)
#define GEN8_INST_DEPCTRL__MASK					0x00000600
#define GEN8_INST_DEPCTRL__SHIFT				9
#define GEN6_INST_ACCESSMODE__MASK				0x00000100
#define GEN6_INST_ACCESSMODE__SHIFT				8
#define GEN6_INST_OPCODE__MASK					0x0000007f
#define GEN6_INST_OPCODE__SHIFT					0
#define GEN6_INST_DST_ADDRMODE__MASK				0x80000000
#define GEN6_INST_DST_ADDRMODE__SHIFT				31
#define GEN6_INST_DST_HORZSTRIDE__MASK				0x60000000
#define GEN6_INST_DST_HORZSTRIDE__SHIFT				29
#define GEN6_INST_DST_REG__MASK					0x1fe00000
#define GEN6_INST_DST_REG__SHIFT				21
#define GEN6_INST_DST_SUBREG__MASK				0x001f0000
#define GEN6_INST_DST_SUBREG__SHIFT				16
#define GEN6_INST_DST_ADDR_SUBREG__MASK				0x1c000000
#define GEN6_INST_DST_ADDR_SUBREG__SHIFT			26
#define GEN6_INST_DST_ADDR_IMM__MASK				0x03ff0000
#define GEN6_INST_DST_ADDR_IMM__SHIFT				16
#define GEN8_INST_DST_ADDR_SUBREG__MASK				0x1e000000
#define GEN8_INST_DST_ADDR_SUBREG__SHIFT			25
#define GEN8_INST_DST_ADDR_IMM__MASK				0x01ff0000
#define GEN8_INST_DST_ADDR_IMM__SHIFT				16
#define GEN6_INST_DST_SUBREG_ALIGN16__MASK			0x00100000
#define GEN6_INST_DST_SUBREG_ALIGN16__SHIFT			20
#define GEN6_INST_DST_SUBREG_ALIGN16__SHR			4
#define GEN6_INST_DST_ADDR_IMM_ALIGN16__MASK			0x03f00000
#define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHIFT			20
#define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR			4
#define GEN8_INST_DST_ADDR_IMM_ALIGN16__MASK			0x01f00000
#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHIFT			20
#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHR			4
#define GEN6_INST_DST_WRITEMASK__MASK				0x000f0000
#define GEN6_INST_DST_WRITEMASK__SHIFT				16
#define GEN7_INST_NIBCTRL					(0x1 << 15)
#define GEN6_INST_SRC1_TYPE__MASK				0x00007000
#define GEN6_INST_SRC1_TYPE__SHIFT				12
#define GEN6_INST_SRC1_FILE__MASK				0x00000c00
#define GEN6_INST_SRC1_FILE__SHIFT				10
#define GEN6_INST_SRC0_TYPE__MASK				0x00000380
#define GEN6_INST_SRC0_TYPE__SHIFT				7
#define GEN6_INST_SRC0_FILE__MASK				0x00000060
#define GEN6_INST_SRC0_FILE__SHIFT				5
#define GEN6_INST_DST_TYPE__MASK				0x0000001c
#define GEN6_INST_DST_TYPE__SHIFT				2
#define GEN6_INST_DST_FILE__MASK				0x00000003
#define GEN6_INST_DST_FILE__SHIFT				0
#define GEN8_INST_DST_ADDR_IMM_BIT9__MASK			0x00008000
#define GEN8_INST_DST_ADDR_IMM_BIT9__SHIFT			15
#define GEN8_INST_DST_ADDR_IMM_BIT9__SHR			9
#define GEN8_INST_SRC0_TYPE__MASK				0x00007800
#define GEN8_INST_SRC0_TYPE__SHIFT				11
#define GEN8_INST_SRC0_FILE__MASK				0x00000600
#define GEN8_INST_SRC0_FILE__SHIFT				9
#define GEN8_INST_DST_TYPE__MASK				0x000001e0
#define GEN8_INST_DST_TYPE__SHIFT				5
#define GEN8_INST_DST_FILE__MASK				0x00000018
#define GEN8_INST_DST_FILE__SHIFT				3
#define GEN8_INST_MASKCTRL__MASK				0x00000004
#define GEN8_INST_MASKCTRL__SHIFT				2
#define GEN8_INST_FLAG_REG__MASK				0x00000002
#define GEN8_INST_FLAG_REG__SHIFT				1
#define GEN8_INST_FLAG_SUBREG__MASK				0x00000001
#define GEN8_INST_FLAG_SUBREG__SHIFT				0
#define GEN7_INST_FLAG_REG__MASK				0x04000000
#define GEN7_INST_FLAG_REG__SHIFT				26
#define GEN6_INST_FLAG_SUBREG__MASK				0x02000000
#define GEN6_INST_FLAG_SUBREG__SHIFT				25
#define GEN8_INST_SRC0_ADDR_IMM_BIT9__MASK			0x80000000
#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHIFT			31
#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHR			9
#define GEN8_INST_SRC1_TYPE__MASK				0x78000000
#define GEN8_INST_SRC1_TYPE__SHIFT				27
#define GEN8_INST_SRC1_FILE__MASK				0x06000000
#define GEN8_INST_SRC1_FILE__SHIFT				25
#define GEN8_INST_SRC1_ADDR_IMM_BIT9__MASK			0x02000000
#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHIFT			25
#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHR			9
#define GEN6_INST_SRC_VERTSTRIDE__MASK				0x01e00000
#define GEN6_INST_SRC_VERTSTRIDE__SHIFT				21
#define GEN6_INST_SRC_WIDTH__MASK				0x001c0000
#define GEN6_INST_SRC_WIDTH__SHIFT				18
#define GEN6_INST_SRC_HORZSTRIDE__MASK				0x00030000
#define GEN6_INST_SRC_HORZSTRIDE__SHIFT				16
#define GEN6_INST_SRC_SWIZZLE_W__MASK				0x000c0000
#define GEN6_INST_SRC_SWIZZLE_W__SHIFT				18
#define GEN6_INST_SRC_SWIZZLE_Z__MASK				0x00030000
#define GEN6_INST_SRC_SWIZZLE_Z__SHIFT				16
#define GEN6_INST_SRC_ADDRMODE__MASK				0x00008000
#define GEN6_INST_SRC_ADDRMODE__SHIFT				15
#define GEN6_INST_SRC_NEGATE					(0x1 << 14)
#define GEN6_INST_SRC_ABSOLUTE					(0x1 << 13)
#define GEN6_INST_SRC_REG__MASK					0x00001fe0
#define GEN6_INST_SRC_REG__SHIFT				5
#define GEN6_INST_SRC_SUBREG__MASK				0x0000001f
#define GEN6_INST_SRC_SUBREG__SHIFT				0
#define GEN6_INST_SRC_ADDR_SUBREG__MASK				0x00001c00
#define GEN6_INST_SRC_ADDR_SUBREG__SHIFT			10
#define GEN6_INST_SRC_ADDR_IMM__MASK				0x000003ff
#define GEN6_INST_SRC_ADDR_IMM__SHIFT				0
#define GEN8_INST_SRC_ADDR_SUBREG__MASK				0x00001e00
#define GEN8_INST_SRC_ADDR_SUBREG__SHIFT			9
#define GEN8_INST_SRC_ADDR_IMM__MASK				0x000001ff
#define GEN8_INST_SRC_ADDR_IMM__SHIFT				0
#define GEN6_INST_SRC_SUBREG_ALIGN16__MASK			0x00000010
#define GEN6_INST_SRC_SUBREG_ALIGN16__SHIFT			4
#define GEN6_INST_SRC_SUBREG_ALIGN16__SHR			4
#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__MASK			0x000003f0
#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHIFT			4
#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR			4
#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__MASK			0x000001f0
#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHIFT			4
#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHR			4
#define GEN6_INST_SRC_SWIZZLE_Y__MASK				0x0000000c
#define GEN6_INST_SRC_SWIZZLE_Y__SHIFT				2
#define GEN6_INST_SRC_SWIZZLE_X__MASK				0x00000003
#define GEN6_INST_SRC_SWIZZLE_X__SHIFT				0
#define GEN6_3SRC_DST_REG__MASK					0xff000000
#define GEN6_3SRC_DST_REG__SHIFT				24
#define GEN6_3SRC_DST_SUBREG__MASK				0x00e00000
#define GEN6_3SRC_DST_SUBREG__SHIFT				21
#define GEN6_3SRC_DST_SUBREG__SHR				2
#define GEN6_3SRC_DST_WRITEMASK__MASK				0x001e0000
#define GEN6_3SRC_DST_WRITEMASK__SHIFT				17
#define GEN7_3SRC_NIBCTRL					(0x1 << 15)
#define GEN7_3SRC_DST_TYPE__MASK				0x00003000
#define GEN7_3SRC_DST_TYPE__SHIFT				12
#define GEN7_3SRC_SRC_TYPE__MASK				0x00000c00
#define GEN7_3SRC_SRC_TYPE__SHIFT				10
#define GEN6_3SRC_SRC2_NEGATE					(0x1 << 9)
#define GEN6_3SRC_SRC2_ABSOLUTE					(0x1 << 8)
#define GEN6_3SRC_SRC1_NEGATE					(0x1 << 7)
#define GEN6_3SRC_SRC1_ABSOLUTE					(0x1 << 6)
#define GEN6_3SRC_SRC0_NEGATE					(0x1 << 5)
#define GEN6_3SRC_SRC0_ABSOLUTE					(0x1 << 4)
#define GEN7_3SRC_FLAG_REG__MASK				0x00000004
#define GEN7_3SRC_FLAG_REG__SHIFT				2
#define GEN6_3SRC_FLAG_SUBREG__MASK				0x00000002
#define GEN6_3SRC_FLAG_SUBREG__SHIFT				1
#define GEN6_3SRC_DST_FILE_MRF					(0x1 << 0)
#define GEN8_3SRC_DST_TYPE__MASK				0x0001c000
#define GEN8_3SRC_DST_TYPE__SHIFT				14
#define GEN8_3SRC_SRC_TYPE__MASK				0x00003800
#define GEN8_3SRC_SRC_TYPE__SHIFT				11
#define GEN8_3SRC_SRC2_NEGATE					(0x1 << 10)
#define GEN8_3SRC_SRC2_ABSOLUTE					(0x1 << 9)
#define GEN8_3SRC_SRC1_NEGATE					(0x1 << 8)
#define GEN8_3SRC_SRC1_ABSOLUTE					(0x1 << 7)
#define GEN8_3SRC_SRC0_NEGATE					(0x1 << 6)
#define GEN8_3SRC_SRC0_ABSOLUTE					(0x1 << 5)
#define GEN8_3SRC_MASKCTRL__MASK				0x00000004
#define GEN8_3SRC_MASKCTRL__SHIFT				2
#define GEN8_3SRC_FLAG_REG__MASK				0x00000002
#define GEN8_3SRC_FLAG_REG__SHIFT				1
#define GEN8_3SRC_FLAG_SUBREG__MASK				0x00000001
#define GEN8_3SRC_FLAG_SUBREG__SHIFT				0
#define GEN6_3SRC_SRC_REG__MASK					0x000ff000
#define GEN6_3SRC_SRC_REG__SHIFT				12
#define GEN6_3SRC_SRC_SUBREG__MASK				0x00000e00
#define GEN6_3SRC_SRC_SUBREG__SHIFT				9
#define GEN6_3SRC_SRC_SUBREG__SHR				2
#define GEN6_3SRC_SRC_SWIZZLE_W__MASK				0x00000180
#define GEN6_3SRC_SRC_SWIZZLE_W__SHIFT				7
#define GEN6_3SRC_SRC_SWIZZLE_Z__MASK				0x00000060
#define GEN6_3SRC_SRC_SWIZZLE_Z__SHIFT				5
#define GEN6_3SRC_SRC_SWIZZLE_Y__MASK				0x00000018
#define GEN6_3SRC_SRC_SWIZZLE_Y__SHIFT				3
#define GEN6_3SRC_SRC_SWIZZLE_X__MASK				0x00000006
#define GEN6_3SRC_SRC_SWIZZLE_X__SHIFT				1
#define GEN6_3SRC_SRC_REPCTRL					(0x1 << 0)
#define GEN6_COMPACT_SRC1_REG__MASK			0xff00000000000000ULL
#define GEN6_COMPACT_SRC1_REG__SHIFT				56
#define GEN6_COMPACT_SRC0_REG__MASK			0x00ff000000000000ULL
#define GEN6_COMPACT_SRC0_REG__SHIFT				48
#define GEN6_COMPACT_DST_REG__MASK			0x0000ff0000000000ULL
#define GEN6_COMPACT_DST_REG__SHIFT				40
#define GEN6_COMPACT_SRC1_INDEX__MASK			0x000000f800000000ULL
#define GEN6_COMPACT_SRC1_INDEX__SHIFT				35
#define GEN6_COMPACT_SRC0_INDEX__MASK			0x00000007c0000000ULL
#define GEN6_COMPACT_SRC0_INDEX__SHIFT				30
#define GEN6_COMPACT_CMPTCTRL					(0x1 << 29)
#define GEN6_COMPACT_FLAG_SUBREG__MASK				0x10000000
#define GEN6_COMPACT_FLAG_SUBREG__SHIFT				28
#define GEN6_COMPACT_CONDMODIFIER__MASK				0x0f000000
#define GEN6_COMPACT_CONDMODIFIER__SHIFT			24
#define GEN6_COMPACT_ACCWRCTRL					(0x1 << 23)
#define GEN6_COMPACT_SUBREG_INDEX__MASK				0x007c0000
#define GEN6_COMPACT_SUBREG_INDEX__SHIFT			18
#define GEN6_COMPACT_DATATYPE_INDEX__MASK			0x0003e000
#define GEN6_COMPACT_DATATYPE_INDEX__SHIFT			13
#define GEN6_COMPACT_CONTROL_INDEX__MASK			0x00001f00
#define GEN6_COMPACT_CONTROL_INDEX__SHIFT			8
#define GEN6_COMPACT_DEBUGCTRL					(0x1 << 7)
#define GEN6_COMPACT_OPCODE__MASK				0x0000007f
#define GEN6_COMPACT_OPCODE__SHIFT				0
#define GEN8_COMPACT_3SRC_SRC2_REG__MASK		0xfe00000000000000ULL
#define GEN8_COMPACT_3SRC_SRC2_REG__SHIFT			57
#define GEN8_COMPACT_3SRC_SRC2_REG__SHR				1
#define GEN8_COMPACT_3SRC_SRC1_REG__MASK		0x01fc000000000000ULL
#define GEN8_COMPACT_3SRC_SRC1_REG__SHIFT			50
#define GEN8_COMPACT_3SRC_SRC1_REG__SHR				1
#define GEN8_COMPACT_3SRC_SRC0_REG__MASK		0x0003f80000000000ULL
#define GEN8_COMPACT_3SRC_SRC0_REG__SHIFT			43
#define GEN8_COMPACT_3SRC_SRC0_REG__SHR				1
#define GEN8_COMPACT_3SRC_SRC2_SUBREG__MASK		0x0000070000000000ULL
#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHIFT			40
#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHR			2
#define GEN8_COMPACT_3SRC_SRC1_SUBREG__MASK		0x000000e000000000ULL
#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHIFT			37
#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHR			2
#define GEN8_COMPACT_3SRC_SRC0_SUBREG__MASK		0x0000001c00000000ULL
#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHIFT			34
#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHR			2
#define GEN8_COMPACT_3SRC_SRC2_REPCTRL				(0x1ULL << 33)
#define GEN8_COMPACT_3SRC_SRC1_REPCTRL				(0x1ULL << 32)
#define GEN8_COMPACT_3SRC_SATURATE				(0x1 << 31)
#define GEN8_COMPACT_3SRC_DEBUGCTRL				(0x1 << 30)
#define GEN8_COMPACT_3SRC_CMPTCTRL				(0x1 << 29)
#define GEN8_COMPACT_3SRC_SRC0_REPCTRL				(0x1 << 28)
#define GEN8_COMPACT_3SRC_DST_REG__MASK				0x0007f000
#define GEN8_COMPACT_3SRC_DST_REG__SHIFT			12
#define GEN8_COMPACT_3SRC_SOURCE_INDEX__MASK			0x00000c00
#define GEN8_COMPACT_3SRC_SOURCE_INDEX__SHIFT			10
#define GEN8_COMPACT_3SRC_CONTROL_INDEX__MASK			0x00000300
#define GEN8_COMPACT_3SRC_CONTROL_INDEX__SHIFT			8
#define GEN8_COMPACT_3SRC_OPCODE__MASK				0x0000007f
#define GEN8_COMPACT_3SRC_OPCODE__SHIFT				0








#define GEN6_3SRC_SRC_2__MASK				0x7ffffc0000000000ULL
#define GEN6_3SRC_SRC_2__SHIFT					42
#define GEN6_3SRC_SRC_1__MASK				0x000003ffffe00000ULL
#define GEN6_3SRC_SRC_1__SHIFT					21
#define GEN6_3SRC_SRC_0__MASK					0x001fffff
#define GEN6_3SRC_SRC_0__SHIFT					0






#endif /* GEN_EU_ISA_XML */
