/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_pri_crit_l2_regs_3.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:16p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:45 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:16p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_PRI_CRIT_L2_REGS_3_H__
#define BCHP_PRI_CRIT_L2_REGS_3_H__

/***************************************************************************
 *PRI_CRIT_L2_REGS_3 - PRIMARY_ARB_CLIENTS L2 (Mips) critical interrupt controller 3 registers
 ***************************************************************************/
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS       0x0040c480 /* CPU interrupt Status Register */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET          0x0040c484 /* CPU interrupt Set Register */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR        0x0040c488 /* CPU interrupt Clear Register */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS  0x0040c48c /* CPU interrupt Mask Status Register */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET     0x0040c490 /* CPU interrupt Mask Set Register */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR   0x0040c494 /* CPU interrupt Mask Clear Register */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS       0x0040c498 /* PCI interrupt Status Register */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET          0x0040c49c /* PCI interrupt Set Register */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR        0x0040c4a0 /* PCI interrupt Clear Register */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS  0x0040c4a4 /* PCI interrupt Mask Status Register */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET     0x0040c4a8 /* PCI interrupt Mask Set Register */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR   0x0040c4ac /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: CPU_STATUS :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS_reserved0_MASK          0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS_reserved0_SHIFT         0

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: CPU_SET :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET_reserved0_MASK             0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET_reserved0_SHIFT            0

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: CPU_CLEAR :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR_reserved0_MASK           0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR_reserved0_SHIFT          0

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: CPU_MASK_STATUS :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS_reserved0_MASK     0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS_reserved0_SHIFT    0

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: CPU_MASK_SET :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET_reserved0_MASK        0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET_reserved0_SHIFT       0

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: CPU_MASK_CLEAR :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR_reserved0_MASK      0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR_reserved0_SHIFT     0

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: PCI_STATUS :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS_reserved0_MASK          0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS_reserved0_SHIFT         0

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: PCI_SET :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET_reserved0_MASK             0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET_reserved0_SHIFT            0

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: PCI_CLEAR :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR_reserved0_MASK           0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR_reserved0_SHIFT          0

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: PCI_MASK_STATUS :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS_reserved0_MASK     0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS_reserved0_SHIFT    0

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: PCI_MASK_SET :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET_reserved0_MASK        0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET_reserved0_SHIFT       0

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* PRI_CRIT_L2_REGS_3 :: PCI_MASK_CLEAR :: reserved0 [31:00] */
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR_reserved0_MASK      0xffffffff
#define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR_reserved0_SHIFT     0

#endif /* #ifndef BCHP_PRI_CRIT_L2_REGS_3_H__ */

/* End of File */
