/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_sun_l2.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:20p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:43 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:20p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_SUN_L2_H__
#define BCHP_SUN_L2_H__

/***************************************************************************
 *SUN_L2 - Registers for the Sundry block's L2 interrupt controller
 ***************************************************************************/
#define BCHP_SUN_L2_CPU_STATUS                   0x00401800 /* CPU interrupt Status Register */
#define BCHP_SUN_L2_CPU_SET                      0x00401804 /* CPU interrupt Set Register */
#define BCHP_SUN_L2_CPU_CLEAR                    0x00401808 /* CPU interrupt Clear Register */
#define BCHP_SUN_L2_CPU_MASK_STATUS              0x0040180c /* CPU interrupt Mask Status Register */
#define BCHP_SUN_L2_CPU_MASK_SET                 0x00401810 /* CPU interrupt Mask Set Register */
#define BCHP_SUN_L2_CPU_MASK_CLEAR               0x00401814 /* CPU interrupt Mask Clear Register */
#define BCHP_SUN_L2_PCI_STATUS                   0x00401818 /* PCI interrupt Status Register */
#define BCHP_SUN_L2_PCI_SET                      0x0040181c /* PCI interrupt Set Register */
#define BCHP_SUN_L2_PCI_CLEAR                    0x00401820 /* PCI interrupt Clear Register */
#define BCHP_SUN_L2_PCI_MASK_STATUS              0x00401824 /* PCI interrupt Mask Status Register */
#define BCHP_SUN_L2_PCI_MASK_SET                 0x00401828 /* PCI interrupt Mask Set Register */
#define BCHP_SUN_L2_PCI_MASK_CLEAR               0x0040182c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_31_MASK                  0x80000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_31_SHIFT                 31

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_30_MASK                  0x40000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_30_SHIFT                 30

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_29_MASK                  0x20000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_29_SHIFT                 29

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_28_MASK                  0x10000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_28_SHIFT                 28

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_27_MASK                  0x08000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_27_SHIFT                 27

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_26_MASK                  0x04000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_26_SHIFT                 26

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_25_MASK                  0x02000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_25_SHIFT                 25

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_24_MASK                  0x01000000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_24_SHIFT                 24

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_23_MASK                  0x00800000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_23_SHIFT                 23

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_22_MASK                  0x00400000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_22_SHIFT                 22

/* SUN_L2 :: CPU_STATUS :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_21_MASK                  0x00200000
#define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_21_SHIFT                 21

/* SUN_L2 :: CPU_STATUS :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_CPU_STATUS_JTAG_GISB_RG_ERROR_MASK             0x00100000
#define BCHP_SUN_L2_CPU_STATUS_JTAG_GISB_RG_ERROR_SHIFT            20

/* SUN_L2 :: CPU_STATUS :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_CPU_STATUS_AUX_INTR_MASK                       0x00080000
#define BCHP_SUN_L2_CPU_STATUS_AUX_INTR_SHIFT                      19

/* SUN_L2 :: CPU_STATUS :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_CPU_STATUS_SERS_PKT_ERR_MASK                   0x00040000
#define BCHP_SUN_L2_CPU_STATUS_SERS_PKT_ERR_SHIFT                  18

/* SUN_L2 :: CPU_STATUS :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_CPU_STATUS_SERS_CLK_ERR_MASK                   0x00020000
#define BCHP_SUN_L2_CPU_STATUS_SERS_CLK_ERR_SHIFT                  17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_reserved0_MASK        0x00010000
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_reserved0_SHIFT       16

/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK   0x00008000
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT  15

/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK       0x00002000
#define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT      13

/* SUN_L2 :: CPU_STATUS :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_CPU_STATUS_SERS_R_PKT_MASK                     0x00001000
#define BCHP_SUN_L2_CPU_STATUS_SERS_R_PKT_SHIFT                    12

/* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_DISABLE_INTR_MASK        0x00000800
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT       11

/* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK       0x00000400
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT      10

/* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK        0x00000200
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT       9

/* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_DISABLE_INTR_MASK        0x00000100
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT       8

/* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK       0x00000080
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT      7

/* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK        0x00000040
#define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT       6

/* SUN_L2 :: CPU_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_CPU_STATUS_FRONT_PANEL_RESET_INTR_MASK         0x00000020
#define BCHP_SUN_L2_CPU_STATUS_FRONT_PANEL_RESET_INTR_SHIFT        5

/* SUN_L2 :: CPU_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_CPU_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK      0x00000010
#define BCHP_SUN_L2_CPU_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT     4

/* SUN_L2 :: CPU_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_CPU_STATUS_RGR_BRIDGE_ERROR_INTR_MASK          0x00000008
#define BCHP_SUN_L2_CPU_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT         3

/* SUN_L2 :: CPU_STATUS :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_CPU_STATUS_GISB_TEA_INTR_MASK                  0x00000004
#define BCHP_SUN_L2_CPU_STATUS_GISB_TEA_INTR_SHIFT                 2

/* SUN_L2 :: CPU_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_CPU_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK     0x00000002
#define BCHP_SUN_L2_CPU_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT    1

/* SUN_L2 :: CPU_STATUS :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_CPU_STATUS_GISB_TIMEOUT_INTR_MASK              0x00000001
#define BCHP_SUN_L2_CPU_STATUS_GISB_TIMEOUT_INTR_SHIFT             0

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* SUN_L2 :: CPU_SET :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_31_MASK                     0x80000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_31_SHIFT                    31

/* SUN_L2 :: CPU_SET :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_30_MASK                     0x40000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_30_SHIFT                    30

/* SUN_L2 :: CPU_SET :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_29_MASK                     0x20000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_29_SHIFT                    29

/* SUN_L2 :: CPU_SET :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_28_MASK                     0x10000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_28_SHIFT                    28

/* SUN_L2 :: CPU_SET :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_27_MASK                     0x08000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_27_SHIFT                    27

/* SUN_L2 :: CPU_SET :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_26_MASK                     0x04000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_26_SHIFT                    26

/* SUN_L2 :: CPU_SET :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_25_MASK                     0x02000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_25_SHIFT                    25

/* SUN_L2 :: CPU_SET :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_24_MASK                     0x01000000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_24_SHIFT                    24

/* SUN_L2 :: CPU_SET :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_23_MASK                     0x00800000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_23_SHIFT                    23

/* SUN_L2 :: CPU_SET :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_22_MASK                     0x00400000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_22_SHIFT                    22

/* SUN_L2 :: CPU_SET :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_21_MASK                     0x00200000
#define BCHP_SUN_L2_CPU_SET_SPARE_INTR_21_SHIFT                    21

/* SUN_L2 :: CPU_SET :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_CPU_SET_JTAG_GISB_RG_ERROR_MASK                0x00100000
#define BCHP_SUN_L2_CPU_SET_JTAG_GISB_RG_ERROR_SHIFT               20

/* SUN_L2 :: CPU_SET :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_CPU_SET_AUX_INTR_MASK                          0x00080000
#define BCHP_SUN_L2_CPU_SET_AUX_INTR_SHIFT                         19

/* SUN_L2 :: CPU_SET :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_CPU_SET_SERS_PKT_ERR_MASK                      0x00040000
#define BCHP_SUN_L2_CPU_SET_SERS_PKT_ERR_SHIFT                     18

/* SUN_L2 :: CPU_SET :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_CPU_SET_SERS_CLK_ERR_MASK                      0x00020000
#define BCHP_SUN_L2_CPU_SET_SERS_CLK_ERR_SHIFT                     17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT4_MASK    0x00010000
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT   16

/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT3_MASK    0x00008000
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT   15

/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT2_MASK    0x00004000
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT   14

/* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT1_MASK    0x00002000
#define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT   13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_reserved0_MASK           0x00010000
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_reserved0_SHIFT          16

/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK      0x00008000
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT     15

/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_W_PKT_MASK          0x00002000
#define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT         13

/* SUN_L2 :: CPU_SET :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_CPU_SET_SERS_R_PKT_MASK                        0x00001000
#define BCHP_SUN_L2_CPU_SET_SERS_R_PKT_SHIFT                       12

/* SUN_L2 :: CPU_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_DISABLE_INTR_MASK           0x00000800
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_DISABLE_INTR_SHIFT          11

/* SUN_L2 :: CPU_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_WR_ERROR_INTR_MASK          0x00000400
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT         10

/* SUN_L2 :: CPU_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_TIMEOUT_INTR_MASK           0x00000200
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT          9

/* SUN_L2 :: CPU_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_DISABLE_INTR_MASK           0x00000100
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_DISABLE_INTR_SHIFT          8

/* SUN_L2 :: CPU_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_WR_ERROR_INTR_MASK          0x00000080
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT         7

/* SUN_L2 :: CPU_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_TIMEOUT_INTR_MASK           0x00000040
#define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT          6

/* SUN_L2 :: CPU_SET :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_CPU_SET_FRONT_PANEL_RESET_INTR_MASK            0x00000020
#define BCHP_SUN_L2_CPU_SET_FRONT_PANEL_RESET_INTR_SHIFT           5

/* SUN_L2 :: CPU_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_CPU_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK         0x00000010
#define BCHP_SUN_L2_CPU_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT        4

/* SUN_L2 :: CPU_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_CPU_SET_RGR_BRIDGE_ERROR_INTR_MASK             0x00000008
#define BCHP_SUN_L2_CPU_SET_RGR_BRIDGE_ERROR_INTR_SHIFT            3

/* SUN_L2 :: CPU_SET :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_CPU_SET_GISB_TEA_INTR_MASK                     0x00000004
#define BCHP_SUN_L2_CPU_SET_GISB_TEA_INTR_SHIFT                    2

/* SUN_L2 :: CPU_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_CPU_SET_GISB_BREAKPOINT_ERROR_INTR_MASK        0x00000002
#define BCHP_SUN_L2_CPU_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT       1

/* SUN_L2 :: CPU_SET :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_CPU_SET_GISB_TIMEOUT_INTR_MASK                 0x00000001
#define BCHP_SUN_L2_CPU_SET_GISB_TIMEOUT_INTR_SHIFT                0

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_31_MASK                   0x80000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_31_SHIFT                  31

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_30_MASK                   0x40000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_30_SHIFT                  30

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_29_MASK                   0x20000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_29_SHIFT                  29

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_28_MASK                   0x10000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_28_SHIFT                  28

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_27_MASK                   0x08000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_27_SHIFT                  27

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_26_MASK                   0x04000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_26_SHIFT                  26

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_25_MASK                   0x02000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_25_SHIFT                  25

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_24_MASK                   0x01000000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_24_SHIFT                  24

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_23_MASK                   0x00800000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_23_SHIFT                  23

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_22_MASK                   0x00400000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_22_SHIFT                  22

/* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_21_MASK                   0x00200000
#define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_21_SHIFT                  21

/* SUN_L2 :: CPU_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_CPU_CLEAR_JTAG_GISB_RG_ERROR_MASK              0x00100000
#define BCHP_SUN_L2_CPU_CLEAR_JTAG_GISB_RG_ERROR_SHIFT             20

/* SUN_L2 :: CPU_CLEAR :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_CPU_CLEAR_AUX_INTR_MASK                        0x00080000
#define BCHP_SUN_L2_CPU_CLEAR_AUX_INTR_SHIFT                       19

/* SUN_L2 :: CPU_CLEAR :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_CPU_CLEAR_SERS_PKT_ERR_MASK                    0x00040000
#define BCHP_SUN_L2_CPU_CLEAR_SERS_PKT_ERR_SHIFT                   18

/* SUN_L2 :: CPU_CLEAR :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_CPU_CLEAR_SERS_CLK_ERR_MASK                    0x00020000
#define BCHP_SUN_L2_CPU_CLEAR_SERS_CLK_ERR_SHIFT                   17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK  0x00010000
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK  0x00008000
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK  0x00004000
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK  0x00002000
#define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_reserved0_MASK         0x00010000
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_reserved0_SHIFT        16

/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK    0x00008000
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT   15

/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK        0x00002000
#define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT       13

/* SUN_L2 :: CPU_CLEAR :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_CPU_CLEAR_SERS_R_PKT_MASK                      0x00001000
#define BCHP_SUN_L2_CPU_CLEAR_SERS_R_PKT_SHIFT                     12

/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK         0x00000800
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT        11

/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK        0x00000400
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT       10

/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK         0x00000200
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT        9

/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK         0x00000100
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT        8

/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK        0x00000080
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT       7

/* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK         0x00000040
#define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT        6

/* SUN_L2 :: CPU_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_CPU_CLEAR_FRONT_PANEL_RESET_INTR_MASK          0x00000020
#define BCHP_SUN_L2_CPU_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT         5

/* SUN_L2 :: CPU_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_CPU_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK       0x00000010
#define BCHP_SUN_L2_CPU_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT      4

/* SUN_L2 :: CPU_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_CPU_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK           0x00000008
#define BCHP_SUN_L2_CPU_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT          3

/* SUN_L2 :: CPU_CLEAR :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_CPU_CLEAR_GISB_TEA_INTR_MASK                   0x00000004
#define BCHP_SUN_L2_CPU_CLEAR_GISB_TEA_INTR_SHIFT                  2

/* SUN_L2 :: CPU_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_CPU_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK      0x00000002
#define BCHP_SUN_L2_CPU_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT     1

/* SUN_L2 :: CPU_CLEAR :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_CPU_CLEAR_GISB_TIMEOUT_INTR_MASK               0x00000001
#define BCHP_SUN_L2_CPU_CLEAR_GISB_TIMEOUT_INTR_SHIFT              0

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_31_MASK             0x80000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_31_SHIFT            31

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_30_MASK             0x40000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_30_SHIFT            30

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_29_MASK             0x20000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_29_SHIFT            29

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_28_MASK             0x10000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_28_SHIFT            28

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_27_MASK             0x08000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_27_SHIFT            27

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_26_MASK             0x04000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_26_SHIFT            26

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_25_MASK             0x02000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_25_SHIFT            25

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_24_MASK             0x01000000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_24_SHIFT            24

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_23_MASK             0x00800000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_23_SHIFT            23

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_22_MASK             0x00400000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_22_SHIFT            22

/* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_21_MASK             0x00200000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_21_SHIFT            21

/* SUN_L2 :: CPU_MASK_STATUS :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_JTAG_GISB_RG_ERROR_MASK        0x00100000
#define BCHP_SUN_L2_CPU_MASK_STATUS_JTAG_GISB_RG_ERROR_SHIFT       20

/* SUN_L2 :: CPU_MASK_STATUS :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_AUX_INTR_MASK                  0x00080000
#define BCHP_SUN_L2_CPU_MASK_STATUS_AUX_INTR_SHIFT                 19

/* SUN_L2 :: CPU_MASK_STATUS :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_PKT_ERR_MASK              0x00040000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_PKT_ERR_SHIFT             18

/* SUN_L2 :: CPU_MASK_STATUS :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_CLK_ERR_MASK              0x00020000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_CLK_ERR_SHIFT             17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_reserved0_MASK   0x00010000
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_reserved0_SHIFT  16

/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15

/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK  0x00002000
#define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13

/* SUN_L2 :: CPU_MASK_STATUS :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_R_PKT_MASK                0x00001000
#define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_R_PKT_SHIFT               12

/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_MASK   0x00000800
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT  11

/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK  0x00000400
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10

/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK   0x00000200
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT  9

/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_MASK   0x00000100
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT  8

/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK  0x00000080
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7

/* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK   0x00000040
#define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT  6

/* SUN_L2 :: CPU_MASK_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_FRONT_PANEL_RESET_INTR_MASK    0x00000020
#define BCHP_SUN_L2_CPU_MASK_STATUS_FRONT_PANEL_RESET_INTR_SHIFT   5

/* SUN_L2 :: CPU_MASK_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010
#define BCHP_SUN_L2_CPU_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4

/* SUN_L2 :: CPU_MASK_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_MASK     0x00000008
#define BCHP_SUN_L2_CPU_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT    3

/* SUN_L2 :: CPU_MASK_STATUS :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TEA_INTR_MASK             0x00000004
#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TEA_INTR_SHIFT            2

/* SUN_L2 :: CPU_MASK_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002
#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1

/* SUN_L2 :: CPU_MASK_STATUS :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TIMEOUT_INTR_MASK         0x00000001
#define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TIMEOUT_INTR_SHIFT        0

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_31_MASK                0x80000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_31_SHIFT               31

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_30_MASK                0x40000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_30_SHIFT               30

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_29_MASK                0x20000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_29_SHIFT               29

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_28_MASK                0x10000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_28_SHIFT               28

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_27_MASK                0x08000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_27_SHIFT               27

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_26_MASK                0x04000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_26_SHIFT               26

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_25_MASK                0x02000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_25_SHIFT               25

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_24_MASK                0x01000000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_24_SHIFT               24

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_23_MASK                0x00800000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_23_SHIFT               23

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_22_MASK                0x00400000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_22_SHIFT               22

/* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_21_MASK                0x00200000
#define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_21_SHIFT               21

/* SUN_L2 :: CPU_MASK_SET :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_CPU_MASK_SET_JTAG_GISB_RG_ERROR_MASK           0x00100000
#define BCHP_SUN_L2_CPU_MASK_SET_JTAG_GISB_RG_ERROR_SHIFT          20

/* SUN_L2 :: CPU_MASK_SET :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_CPU_MASK_SET_AUX_INTR_MASK                     0x00080000
#define BCHP_SUN_L2_CPU_MASK_SET_AUX_INTR_SHIFT                    19

/* SUN_L2 :: CPU_MASK_SET :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_CPU_MASK_SET_SERS_PKT_ERR_MASK                 0x00040000
#define BCHP_SUN_L2_CPU_MASK_SET_SERS_PKT_ERR_SHIFT                18

/* SUN_L2 :: CPU_MASK_SET :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_CPU_MASK_SET_SERS_CLK_ERR_MASK                 0x00020000
#define BCHP_SUN_L2_CPU_MASK_SET_SERS_CLK_ERR_SHIFT                17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_reserved0_MASK      0x00010000
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_reserved0_SHIFT     16

/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15

/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_W_PKT_MASK     0x00002000
#define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT    13

/* SUN_L2 :: CPU_MASK_SET :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_CPU_MASK_SET_SERS_R_PKT_MASK                   0x00001000
#define BCHP_SUN_L2_CPU_MASK_SET_SERS_R_PKT_SHIFT                  12

/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_DISABLE_INTR_MASK      0x00000800
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_DISABLE_INTR_SHIFT     11

/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_MASK     0x00000400
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT    10

/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_MASK      0x00000200
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT     9

/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_DISABLE_INTR_MASK      0x00000100
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_DISABLE_INTR_SHIFT     8

/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_MASK     0x00000080
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT    7

/* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_MASK      0x00000040
#define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT     6

/* SUN_L2 :: CPU_MASK_SET :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_CPU_MASK_SET_FRONT_PANEL_RESET_INTR_MASK       0x00000020
#define BCHP_SUN_L2_CPU_MASK_SET_FRONT_PANEL_RESET_INTR_SHIFT      5

/* SUN_L2 :: CPU_MASK_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_CPU_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK    0x00000010
#define BCHP_SUN_L2_CPU_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT   4

/* SUN_L2 :: CPU_MASK_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_CPU_MASK_SET_RGR_BRIDGE_ERROR_INTR_MASK        0x00000008
#define BCHP_SUN_L2_CPU_MASK_SET_RGR_BRIDGE_ERROR_INTR_SHIFT       3

/* SUN_L2 :: CPU_MASK_SET :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TEA_INTR_MASK                0x00000004
#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TEA_INTR_SHIFT               2

/* SUN_L2 :: CPU_MASK_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_CPU_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_MASK   0x00000002
#define BCHP_SUN_L2_CPU_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT  1

/* SUN_L2 :: CPU_MASK_SET :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TIMEOUT_INTR_MASK            0x00000001
#define BCHP_SUN_L2_CPU_MASK_SET_GISB_TIMEOUT_INTR_SHIFT           0

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_31_MASK              0x80000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_31_SHIFT             31

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_30_MASK              0x40000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_30_SHIFT             30

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_29_MASK              0x20000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_29_SHIFT             29

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_28_MASK              0x10000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_28_SHIFT             28

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_27_MASK              0x08000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_27_SHIFT             27

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_26_MASK              0x04000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_26_SHIFT             26

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_25_MASK              0x02000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_25_SHIFT             25

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_24_MASK              0x01000000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_24_SHIFT             24

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_23_MASK              0x00800000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_23_SHIFT             23

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_22_MASK              0x00400000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_22_SHIFT             22

/* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_21_MASK              0x00200000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_21_SHIFT             21

/* SUN_L2 :: CPU_MASK_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_JTAG_GISB_RG_ERROR_MASK         0x00100000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_JTAG_GISB_RG_ERROR_SHIFT        20

/* SUN_L2 :: CPU_MASK_CLEAR :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_AUX_INTR_MASK                   0x00080000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_AUX_INTR_SHIFT                  19

/* SUN_L2 :: CPU_MASK_CLEAR :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_PKT_ERR_MASK               0x00040000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_PKT_ERR_SHIFT              18

/* SUN_L2 :: CPU_MASK_CLEAR :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_CLK_ERR_MASK               0x00020000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_CLK_ERR_SHIFT              17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_reserved0_MASK    0x00010000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_reserved0_SHIFT   16

/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15

/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK   0x00002000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT  13

/* SUN_L2 :: CPU_MASK_CLEAR :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_R_PKT_MASK                 0x00001000
#define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_R_PKT_SHIFT                12

/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK    0x00000800
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT   11

/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK   0x00000400
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT  10

/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK    0x00000200
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT   9

/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK    0x00000100
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT   8

/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK   0x00000080
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT  7

/* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK    0x00000040
#define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT   6

/* SUN_L2 :: CPU_MASK_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_FRONT_PANEL_RESET_INTR_MASK     0x00000020
#define BCHP_SUN_L2_CPU_MASK_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT    5

/* SUN_L2 :: CPU_MASK_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK  0x00000010
#define BCHP_SUN_L2_CPU_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4

/* SUN_L2 :: CPU_MASK_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK      0x00000008
#define BCHP_SUN_L2_CPU_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT     3

/* SUN_L2 :: CPU_MASK_CLEAR :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TEA_INTR_MASK              0x00000004
#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TEA_INTR_SHIFT             2

/* SUN_L2 :: CPU_MASK_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002
#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1

/* SUN_L2 :: CPU_MASK_CLEAR :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TIMEOUT_INTR_MASK          0x00000001
#define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TIMEOUT_INTR_SHIFT         0

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_31_MASK                  0x80000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_31_SHIFT                 31

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_30_MASK                  0x40000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_30_SHIFT                 30

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_29_MASK                  0x20000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_29_SHIFT                 29

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_28_MASK                  0x10000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_28_SHIFT                 28

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_27_MASK                  0x08000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_27_SHIFT                 27

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_26_MASK                  0x04000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_26_SHIFT                 26

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_25_MASK                  0x02000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_25_SHIFT                 25

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_24_MASK                  0x01000000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_24_SHIFT                 24

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_23_MASK                  0x00800000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_23_SHIFT                 23

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_22_MASK                  0x00400000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_22_SHIFT                 22

/* SUN_L2 :: PCI_STATUS :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_21_MASK                  0x00200000
#define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_21_SHIFT                 21

/* SUN_L2 :: PCI_STATUS :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_PCI_STATUS_JTAG_GISB_RG_ERROR_MASK             0x00100000
#define BCHP_SUN_L2_PCI_STATUS_JTAG_GISB_RG_ERROR_SHIFT            20

/* SUN_L2 :: PCI_STATUS :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_PCI_STATUS_AUX_INTR_MASK                       0x00080000
#define BCHP_SUN_L2_PCI_STATUS_AUX_INTR_SHIFT                      19

/* SUN_L2 :: PCI_STATUS :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_PCI_STATUS_SERS_PKT_ERR_MASK                   0x00040000
#define BCHP_SUN_L2_PCI_STATUS_SERS_PKT_ERR_SHIFT                  18

/* SUN_L2 :: PCI_STATUS :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_PCI_STATUS_SERS_CLK_ERR_MASK                   0x00020000
#define BCHP_SUN_L2_PCI_STATUS_SERS_CLK_ERR_SHIFT                  17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_reserved0_MASK        0x00010000
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_reserved0_SHIFT       16

/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK   0x00008000
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT  15

/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK       0x00002000
#define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT      13

/* SUN_L2 :: PCI_STATUS :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_PCI_STATUS_SERS_R_PKT_MASK                     0x00001000
#define BCHP_SUN_L2_PCI_STATUS_SERS_R_PKT_SHIFT                    12

/* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_DISABLE_INTR_MASK        0x00000800
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT       11

/* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK       0x00000400
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT      10

/* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK        0x00000200
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT       9

/* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_DISABLE_INTR_MASK        0x00000100
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT       8

/* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK       0x00000080
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT      7

/* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK        0x00000040
#define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT       6

/* SUN_L2 :: PCI_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_PCI_STATUS_FRONT_PANEL_RESET_INTR_MASK         0x00000020
#define BCHP_SUN_L2_PCI_STATUS_FRONT_PANEL_RESET_INTR_SHIFT        5

/* SUN_L2 :: PCI_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_PCI_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK      0x00000010
#define BCHP_SUN_L2_PCI_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT     4

/* SUN_L2 :: PCI_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_PCI_STATUS_RGR_BRIDGE_ERROR_INTR_MASK          0x00000008
#define BCHP_SUN_L2_PCI_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT         3

/* SUN_L2 :: PCI_STATUS :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_PCI_STATUS_GISB_TEA_INTR_MASK                  0x00000004
#define BCHP_SUN_L2_PCI_STATUS_GISB_TEA_INTR_SHIFT                 2

/* SUN_L2 :: PCI_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_PCI_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK     0x00000002
#define BCHP_SUN_L2_PCI_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT    1

/* SUN_L2 :: PCI_STATUS :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_PCI_STATUS_GISB_TIMEOUT_INTR_MASK              0x00000001
#define BCHP_SUN_L2_PCI_STATUS_GISB_TIMEOUT_INTR_SHIFT             0

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* SUN_L2 :: PCI_SET :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_31_MASK                     0x80000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_31_SHIFT                    31

/* SUN_L2 :: PCI_SET :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_30_MASK                     0x40000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_30_SHIFT                    30

/* SUN_L2 :: PCI_SET :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_29_MASK                     0x20000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_29_SHIFT                    29

/* SUN_L2 :: PCI_SET :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_28_MASK                     0x10000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_28_SHIFT                    28

/* SUN_L2 :: PCI_SET :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_27_MASK                     0x08000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_27_SHIFT                    27

/* SUN_L2 :: PCI_SET :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_26_MASK                     0x04000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_26_SHIFT                    26

/* SUN_L2 :: PCI_SET :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_25_MASK                     0x02000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_25_SHIFT                    25

/* SUN_L2 :: PCI_SET :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_24_MASK                     0x01000000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_24_SHIFT                    24

/* SUN_L2 :: PCI_SET :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_23_MASK                     0x00800000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_23_SHIFT                    23

/* SUN_L2 :: PCI_SET :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_22_MASK                     0x00400000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_22_SHIFT                    22

/* SUN_L2 :: PCI_SET :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_21_MASK                     0x00200000
#define BCHP_SUN_L2_PCI_SET_SPARE_INTR_21_SHIFT                    21

/* SUN_L2 :: PCI_SET :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_PCI_SET_JTAG_GISB_RG_ERROR_MASK                0x00100000
#define BCHP_SUN_L2_PCI_SET_JTAG_GISB_RG_ERROR_SHIFT               20

/* SUN_L2 :: PCI_SET :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_PCI_SET_AUX_INTR_MASK                          0x00080000
#define BCHP_SUN_L2_PCI_SET_AUX_INTR_SHIFT                         19

/* SUN_L2 :: PCI_SET :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_PCI_SET_SERS_PKT_ERR_MASK                      0x00040000
#define BCHP_SUN_L2_PCI_SET_SERS_PKT_ERR_SHIFT                     18

/* SUN_L2 :: PCI_SET :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_PCI_SET_SERS_CLK_ERR_MASK                      0x00020000
#define BCHP_SUN_L2_PCI_SET_SERS_CLK_ERR_SHIFT                     17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT4_MASK    0x00010000
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT   16

/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT3_MASK    0x00008000
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT   15

/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT2_MASK    0x00004000
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT   14

/* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT1_MASK    0x00002000
#define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT   13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_reserved0_MASK           0x00010000
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_reserved0_SHIFT          16

/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK      0x00008000
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT     15

/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_W_PKT_MASK          0x00002000
#define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT         13

/* SUN_L2 :: PCI_SET :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_PCI_SET_SERS_R_PKT_MASK                        0x00001000
#define BCHP_SUN_L2_PCI_SET_SERS_R_PKT_SHIFT                       12

/* SUN_L2 :: PCI_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_DISABLE_INTR_MASK           0x00000800
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_DISABLE_INTR_SHIFT          11

/* SUN_L2 :: PCI_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_WR_ERROR_INTR_MASK          0x00000400
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT         10

/* SUN_L2 :: PCI_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_TIMEOUT_INTR_MASK           0x00000200
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT          9

/* SUN_L2 :: PCI_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_DISABLE_INTR_MASK           0x00000100
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_DISABLE_INTR_SHIFT          8

/* SUN_L2 :: PCI_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_WR_ERROR_INTR_MASK          0x00000080
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT         7

/* SUN_L2 :: PCI_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_TIMEOUT_INTR_MASK           0x00000040
#define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT          6

/* SUN_L2 :: PCI_SET :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_PCI_SET_FRONT_PANEL_RESET_INTR_MASK            0x00000020
#define BCHP_SUN_L2_PCI_SET_FRONT_PANEL_RESET_INTR_SHIFT           5

/* SUN_L2 :: PCI_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_PCI_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK         0x00000010
#define BCHP_SUN_L2_PCI_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT        4

/* SUN_L2 :: PCI_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_PCI_SET_RGR_BRIDGE_ERROR_INTR_MASK             0x00000008
#define BCHP_SUN_L2_PCI_SET_RGR_BRIDGE_ERROR_INTR_SHIFT            3

/* SUN_L2 :: PCI_SET :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_PCI_SET_GISB_TEA_INTR_MASK                     0x00000004
#define BCHP_SUN_L2_PCI_SET_GISB_TEA_INTR_SHIFT                    2

/* SUN_L2 :: PCI_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_PCI_SET_GISB_BREAKPOINT_ERROR_INTR_MASK        0x00000002
#define BCHP_SUN_L2_PCI_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT       1

/* SUN_L2 :: PCI_SET :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_PCI_SET_GISB_TIMEOUT_INTR_MASK                 0x00000001
#define BCHP_SUN_L2_PCI_SET_GISB_TIMEOUT_INTR_SHIFT                0

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_31_MASK                   0x80000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_31_SHIFT                  31

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_30_MASK                   0x40000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_30_SHIFT                  30

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_29_MASK                   0x20000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_29_SHIFT                  29

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_28_MASK                   0x10000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_28_SHIFT                  28

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_27_MASK                   0x08000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_27_SHIFT                  27

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_26_MASK                   0x04000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_26_SHIFT                  26

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_25_MASK                   0x02000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_25_SHIFT                  25

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_24_MASK                   0x01000000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_24_SHIFT                  24

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_23_MASK                   0x00800000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_23_SHIFT                  23

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_22_MASK                   0x00400000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_22_SHIFT                  22

/* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_21_MASK                   0x00200000
#define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_21_SHIFT                  21

/* SUN_L2 :: PCI_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_PCI_CLEAR_JTAG_GISB_RG_ERROR_MASK              0x00100000
#define BCHP_SUN_L2_PCI_CLEAR_JTAG_GISB_RG_ERROR_SHIFT             20

/* SUN_L2 :: PCI_CLEAR :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_PCI_CLEAR_AUX_INTR_MASK                        0x00080000
#define BCHP_SUN_L2_PCI_CLEAR_AUX_INTR_SHIFT                       19

/* SUN_L2 :: PCI_CLEAR :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_PCI_CLEAR_SERS_PKT_ERR_MASK                    0x00040000
#define BCHP_SUN_L2_PCI_CLEAR_SERS_PKT_ERR_SHIFT                   18

/* SUN_L2 :: PCI_CLEAR :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_PCI_CLEAR_SERS_CLK_ERR_MASK                    0x00020000
#define BCHP_SUN_L2_PCI_CLEAR_SERS_CLK_ERR_SHIFT                   17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK  0x00010000
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK  0x00008000
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK  0x00004000
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK  0x00002000
#define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_reserved0_MASK         0x00010000
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_reserved0_SHIFT        16

/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK    0x00008000
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT   15

/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK        0x00002000
#define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT       13

/* SUN_L2 :: PCI_CLEAR :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_PCI_CLEAR_SERS_R_PKT_MASK                      0x00001000
#define BCHP_SUN_L2_PCI_CLEAR_SERS_R_PKT_SHIFT                     12

/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK         0x00000800
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT        11

/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK        0x00000400
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT       10

/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK         0x00000200
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT        9

/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK         0x00000100
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT        8

/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK        0x00000080
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT       7

/* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK         0x00000040
#define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT        6

/* SUN_L2 :: PCI_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_PCI_CLEAR_FRONT_PANEL_RESET_INTR_MASK          0x00000020
#define BCHP_SUN_L2_PCI_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT         5

/* SUN_L2 :: PCI_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_PCI_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK       0x00000010
#define BCHP_SUN_L2_PCI_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT      4

/* SUN_L2 :: PCI_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_PCI_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK           0x00000008
#define BCHP_SUN_L2_PCI_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT          3

/* SUN_L2 :: PCI_CLEAR :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_PCI_CLEAR_GISB_TEA_INTR_MASK                   0x00000004
#define BCHP_SUN_L2_PCI_CLEAR_GISB_TEA_INTR_SHIFT                  2

/* SUN_L2 :: PCI_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_PCI_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK      0x00000002
#define BCHP_SUN_L2_PCI_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT     1

/* SUN_L2 :: PCI_CLEAR :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_PCI_CLEAR_GISB_TIMEOUT_INTR_MASK               0x00000001
#define BCHP_SUN_L2_PCI_CLEAR_GISB_TIMEOUT_INTR_SHIFT              0

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_31_MASK             0x80000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_31_SHIFT            31

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_30_MASK             0x40000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_30_SHIFT            30

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_29_MASK             0x20000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_29_SHIFT            29

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_28_MASK             0x10000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_28_SHIFT            28

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_27_MASK             0x08000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_27_SHIFT            27

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_26_MASK             0x04000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_26_SHIFT            26

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_25_MASK             0x02000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_25_SHIFT            25

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_24_MASK             0x01000000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_24_SHIFT            24

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_23_MASK             0x00800000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_23_SHIFT            23

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_22_MASK             0x00400000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_22_SHIFT            22

/* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_21_MASK             0x00200000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_21_SHIFT            21

/* SUN_L2 :: PCI_MASK_STATUS :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_JTAG_GISB_RG_ERROR_MASK        0x00100000
#define BCHP_SUN_L2_PCI_MASK_STATUS_JTAG_GISB_RG_ERROR_SHIFT       20

/* SUN_L2 :: PCI_MASK_STATUS :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_AUX_INTR_MASK                  0x00080000
#define BCHP_SUN_L2_PCI_MASK_STATUS_AUX_INTR_SHIFT                 19

/* SUN_L2 :: PCI_MASK_STATUS :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_PKT_ERR_MASK              0x00040000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_PKT_ERR_SHIFT             18

/* SUN_L2 :: PCI_MASK_STATUS :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_CLK_ERR_MASK              0x00020000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_CLK_ERR_SHIFT             17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_reserved0_MASK   0x00010000
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_reserved0_SHIFT  16

/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15

/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK  0x00002000
#define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13

/* SUN_L2 :: PCI_MASK_STATUS :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_R_PKT_MASK                0x00001000
#define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_R_PKT_SHIFT               12

/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_MASK   0x00000800
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT  11

/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK  0x00000400
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10

/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK   0x00000200
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT  9

/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_MASK   0x00000100
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT  8

/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK  0x00000080
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7

/* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK   0x00000040
#define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT  6

/* SUN_L2 :: PCI_MASK_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_FRONT_PANEL_RESET_INTR_MASK    0x00000020
#define BCHP_SUN_L2_PCI_MASK_STATUS_FRONT_PANEL_RESET_INTR_SHIFT   5

/* SUN_L2 :: PCI_MASK_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010
#define BCHP_SUN_L2_PCI_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4

/* SUN_L2 :: PCI_MASK_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_MASK     0x00000008
#define BCHP_SUN_L2_PCI_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT    3

/* SUN_L2 :: PCI_MASK_STATUS :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TEA_INTR_MASK             0x00000004
#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TEA_INTR_SHIFT            2

/* SUN_L2 :: PCI_MASK_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002
#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1

/* SUN_L2 :: PCI_MASK_STATUS :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TIMEOUT_INTR_MASK         0x00000001
#define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TIMEOUT_INTR_SHIFT        0

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_31_MASK                0x80000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_31_SHIFT               31

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_30_MASK                0x40000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_30_SHIFT               30

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_29_MASK                0x20000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_29_SHIFT               29

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_28_MASK                0x10000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_28_SHIFT               28

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_27_MASK                0x08000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_27_SHIFT               27

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_26_MASK                0x04000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_26_SHIFT               26

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_25_MASK                0x02000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_25_SHIFT               25

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_24_MASK                0x01000000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_24_SHIFT               24

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_23_MASK                0x00800000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_23_SHIFT               23

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_22_MASK                0x00400000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_22_SHIFT               22

/* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_21_MASK                0x00200000
#define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_21_SHIFT               21

/* SUN_L2 :: PCI_MASK_SET :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_PCI_MASK_SET_JTAG_GISB_RG_ERROR_MASK           0x00100000
#define BCHP_SUN_L2_PCI_MASK_SET_JTAG_GISB_RG_ERROR_SHIFT          20

/* SUN_L2 :: PCI_MASK_SET :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_PCI_MASK_SET_AUX_INTR_MASK                     0x00080000
#define BCHP_SUN_L2_PCI_MASK_SET_AUX_INTR_SHIFT                    19

/* SUN_L2 :: PCI_MASK_SET :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_PCI_MASK_SET_SERS_PKT_ERR_MASK                 0x00040000
#define BCHP_SUN_L2_PCI_MASK_SET_SERS_PKT_ERR_SHIFT                18

/* SUN_L2 :: PCI_MASK_SET :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_PCI_MASK_SET_SERS_CLK_ERR_MASK                 0x00020000
#define BCHP_SUN_L2_PCI_MASK_SET_SERS_CLK_ERR_SHIFT                17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_reserved0_MASK      0x00010000
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_reserved0_SHIFT     16

/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15

/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_W_PKT_MASK     0x00002000
#define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT    13

/* SUN_L2 :: PCI_MASK_SET :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_PCI_MASK_SET_SERS_R_PKT_MASK                   0x00001000
#define BCHP_SUN_L2_PCI_MASK_SET_SERS_R_PKT_SHIFT                  12

/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_DISABLE_INTR_MASK      0x00000800
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_DISABLE_INTR_SHIFT     11

/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_MASK     0x00000400
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT    10

/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_MASK      0x00000200
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT     9

/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_DISABLE_INTR_MASK      0x00000100
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_DISABLE_INTR_SHIFT     8

/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_MASK     0x00000080
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT    7

/* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_MASK      0x00000040
#define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT     6

/* SUN_L2 :: PCI_MASK_SET :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_PCI_MASK_SET_FRONT_PANEL_RESET_INTR_MASK       0x00000020
#define BCHP_SUN_L2_PCI_MASK_SET_FRONT_PANEL_RESET_INTR_SHIFT      5

/* SUN_L2 :: PCI_MASK_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_PCI_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK    0x00000010
#define BCHP_SUN_L2_PCI_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT   4

/* SUN_L2 :: PCI_MASK_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_PCI_MASK_SET_RGR_BRIDGE_ERROR_INTR_MASK        0x00000008
#define BCHP_SUN_L2_PCI_MASK_SET_RGR_BRIDGE_ERROR_INTR_SHIFT       3

/* SUN_L2 :: PCI_MASK_SET :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TEA_INTR_MASK                0x00000004
#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TEA_INTR_SHIFT               2

/* SUN_L2 :: PCI_MASK_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_PCI_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_MASK   0x00000002
#define BCHP_SUN_L2_PCI_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT  1

/* SUN_L2 :: PCI_MASK_SET :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TIMEOUT_INTR_MASK            0x00000001
#define BCHP_SUN_L2_PCI_MASK_SET_GISB_TIMEOUT_INTR_SHIFT           0

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_31 [31:31] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_31_MASK              0x80000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_31_SHIFT             31

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_30 [30:30] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_30_MASK              0x40000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_30_SHIFT             30

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_29 [29:29] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_29_MASK              0x20000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_29_SHIFT             29

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_28 [28:28] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_28_MASK              0x10000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_28_SHIFT             28

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_27 [27:27] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_27_MASK              0x08000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_27_SHIFT             27

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_26 [26:26] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_26_MASK              0x04000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_26_SHIFT             26

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_25 [25:25] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_25_MASK              0x02000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_25_SHIFT             25

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_24 [24:24] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_24_MASK              0x01000000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_24_SHIFT             24

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_23 [23:23] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_23_MASK              0x00800000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_23_SHIFT             23

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_22 [22:22] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_22_MASK              0x00400000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_22_SHIFT             22

/* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_21 [21:21] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_21_MASK              0x00200000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_21_SHIFT             21

/* SUN_L2 :: PCI_MASK_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_JTAG_GISB_RG_ERROR_MASK         0x00100000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_JTAG_GISB_RG_ERROR_SHIFT        20

/* SUN_L2 :: PCI_MASK_CLEAR :: AUX_INTR [19:19] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_AUX_INTR_MASK                   0x00080000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_AUX_INTR_SHIFT                  19

/* SUN_L2 :: PCI_MASK_CLEAR :: SERS_PKT_ERR [18:18] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_PKT_ERR_MASK               0x00040000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_PKT_ERR_SHIFT              18

/* SUN_L2 :: PCI_MASK_CLEAR :: SERS_CLK_ERR [17:17] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_CLK_ERR_MASK               0x00020000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_CLK_ERR_SHIFT              17

/* union - case mapped_buffer_mode [16:13] */
/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16

/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15

/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14

/* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13

/* union - case cmd_fifo_mode [16:13] */
/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_reserved0_MASK    0x00010000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_reserved0_SHIFT   16

/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15

/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14

/* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK   0x00002000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT  13

/* SUN_L2 :: PCI_MASK_CLEAR :: SERS_R_PKT [12:12] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_R_PKT_MASK                 0x00001000
#define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_R_PKT_SHIFT                12

/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK    0x00000800
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT   11

/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK   0x00000400
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT  10

/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK    0x00000200
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT   9

/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK    0x00000100
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT   8

/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK   0x00000080
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT  7

/* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK    0x00000040
#define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT   6

/* SUN_L2 :: PCI_MASK_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_FRONT_PANEL_RESET_INTR_MASK     0x00000020
#define BCHP_SUN_L2_PCI_MASK_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT    5

/* SUN_L2 :: PCI_MASK_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK  0x00000010
#define BCHP_SUN_L2_PCI_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4

/* SUN_L2 :: PCI_MASK_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK      0x00000008
#define BCHP_SUN_L2_PCI_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT     3

/* SUN_L2 :: PCI_MASK_CLEAR :: GISB_TEA_INTR [02:02] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TEA_INTR_MASK              0x00000004
#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TEA_INTR_SHIFT             2

/* SUN_L2 :: PCI_MASK_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002
#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1

/* SUN_L2 :: PCI_MASK_CLEAR :: GISB_TIMEOUT_INTR [00:00] */
#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TIMEOUT_INTR_MASK          0x00000001
#define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TIMEOUT_INTR_SHIFT         0

#endif /* #ifndef BCHP_SUN_L2_H__ */

/* End of File */
