/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_xpt_bus_if.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:23p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:43:14 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:23p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_XPT_BUS_IF_H__
#define BCHP_XPT_BUS_IF_H__

/***************************************************************************
 *XPT_BUS_IF - Data Transport Configuration Registers
 ***************************************************************************/
#define BCHP_XPT_BUS_IF_MISC_CTRL0               0x00200000 /* Data Transport Misc Control 0 Register */
#define BCHP_XPT_BUS_IF_TEST_MODE                0x00200004 /* Data transport test register */
#define BCHP_XPT_BUS_IF_REV_ID                   0x00200008 /* Data Transport Revision Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG         0x00200038 /* Interrupt Status4 Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN      0x0020003c /* Interrupt Status4 Enable Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG         0x00200040 /* Interrupt Status5 Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN      0x00200044 /* Interrupt Status5 Enable Register */
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG   0x00200048 /* LCIF to XMEMIF Debug Registers */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG   0x0020004c /* LCIF to XMEMIF Debug Registers */
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS            0x00200050 /* Data Transport max number of playbacks supported */
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS         0x00200058 /* Data Transport max number of PID channels supported */
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS        0x00200064 /* Data Transport max number of TPIT channels supported */
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS        0x00200068 /* Data Transport max number of RAVE contexts supported */
#define BCHP_XPT_BUS_IF_MAX_SCDS                 0x00200074 /* Data Transport max number of SCDs supported */

/***************************************************************************
 *MISC_CTRL0 - Data Transport Misc Control 0 Register
 ***************************************************************************/
/* XPT_BUS_IF :: MISC_CTRL0 :: reserved0 [31:03] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_MASK                  0xfffffff8
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_SHIFT                 3

/* XPT_BUS_IF :: MISC_CTRL0 :: ERROR_INT_TEST_MODE [02:02] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_MASK        0x00000004
#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_SHIFT       2

/* XPT_BUS_IF :: MISC_CTRL0 :: reserved1 [01:01] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_MASK                  0x00000002
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_SHIFT                 1

/* XPT_BUS_IF :: MISC_CTRL0 :: LINK_LIST_DESC_ENDIAN_CTRL [00:00] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_MASK 0x00000001
#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_SHIFT 0

/***************************************************************************
 *TEST_MODE - Data transport test register
 ***************************************************************************/
/* XPT_BUS_IF :: TEST_MODE :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_MASK                   0xfffffffe
#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_SHIFT                  1

/* XPT_BUS_IF :: TEST_MODE :: PSG_SECRET_ENBLE [00:00] */
#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_MASK            0x00000001
#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_SHIFT           0

/***************************************************************************
 *REV_ID - Data Transport Revision Register
 ***************************************************************************/
/* XPT_BUS_IF :: REV_ID :: reserved0 [31:16] */
#define BCHP_XPT_BUS_IF_REV_ID_reserved0_MASK                      0xffff0000
#define BCHP_XPT_BUS_IF_REV_ID_reserved0_SHIFT                     16

/* XPT_BUS_IF :: REV_ID :: MAJOR_REV_NUMBER [15:08] */
#define BCHP_XPT_BUS_IF_REV_ID_MAJOR_REV_NUMBER_MASK               0x0000ff00
#define BCHP_XPT_BUS_IF_REV_ID_MAJOR_REV_NUMBER_SHIFT              8

/* XPT_BUS_IF :: REV_ID :: MINOR_REV_NUMBER [07:00] */
#define BCHP_XPT_BUS_IF_REV_ID_MINOR_REV_NUMBER_MASK               0x000000ff
#define BCHP_XPT_BUS_IF_REV_ID_MINOR_REV_NUMBER_SHIFT              0

/***************************************************************************
 *INTR_STATUS4_REG - Interrupt Status4 Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved0 [31:15] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_MASK            0xffff8000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_SHIFT           15

/* XPT_BUS_IF :: INTR_STATUS4_REG :: GISB_BRIDGE [14:14] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_MASK          0x00004000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_SHIFT         14

/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved1 [13:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_MASK            0x00003fff
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_SHIFT           0

/***************************************************************************
 *INTR_STATUS4_REG_EN - Interrupt Status4 Enable Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved0 [31:15] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_MASK         0xffff8000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_SHIFT        15

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: INTR_STATUS4_REG_EN [14:14] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_INTR_STATUS4_REG_EN_MASK 0x00004000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_INTR_STATUS4_REG_EN_SHIFT 14

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved1 [13:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_MASK         0x00003fff
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_SHIFT        0

/***************************************************************************
 *INTR_STATUS5_REG - Interrupt Status5 Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS5_REG :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_MASK            0xfffffffe
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_SHIFT           1

/* XPT_BUS_IF :: INTR_STATUS5_REG :: WRCHECKER_INT [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_MASK        0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_SHIFT       0

/***************************************************************************
 *INTR_STATUS5_REG_EN - Interrupt Status5 Enable Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_MASK         0xfffffffe
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_SHIFT        1

/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: INTR_STATUS5_REG_EN [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_INTR_STATUS5_REG_EN_MASK 0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_INTR_STATUS5_REG_EN_SHIFT 0

/***************************************************************************
 *XMEMIF_RD_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers
 ***************************************************************************/
/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: reserved0 [31:13] */
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved0_MASK      0xffffe000
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved0_SHIFT     13

/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: PB_DEBUG_REG [12:08] */
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_PB_DEBUG_REG_MASK   0x00001f00
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_PB_DEBUG_REG_SHIFT  8

/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: reserved1 [07:00] */
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved1_MASK      0x000000ff
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved1_SHIFT     0

/***************************************************************************
 *XMEMIF_WR_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers
 ***************************************************************************/
/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: reserved0 [31:02] */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_MASK      0xfffffffc
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_SHIFT     2

/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RAVE_DEBUG_REG [01:00] */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_MASK 0x00000003
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_SHIFT 0

/***************************************************************************
 *MAX_PLAYBACKS - Data Transport max number of playbacks supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_PLAYBACKS :: reserved0 [31:04] */
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_MASK               0xfffffff0
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_SHIFT              4

/* XPT_BUS_IF :: MAX_PLAYBACKS :: MAX_PLAYBACKS [03:00] */
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_MASK           0x0000000f
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_SHIFT          0

/***************************************************************************
 *MAX_PID_CHANNELS - Data Transport max number of PID channels supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_PID_CHANNELS :: reserved0 [31:12] */
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_MASK            0xfffff000
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_SHIFT           12

/* XPT_BUS_IF :: MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK     0x00000fff
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT    0

/***************************************************************************
 *MAX_TPIT_CHANNELS - Data Transport max number of TPIT channels supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: reserved0 [31:04] */
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_MASK           0xfffffff0
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_SHIFT          4

/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: MAX_TPIT_CHANNELS [03:00] */
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_MASK   0x0000000f
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_SHIFT  0

/***************************************************************************
 *MAX_RAVE_CONTEXTS - Data Transport max number of RAVE contexts supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: reserved0 [31:08] */
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_MASK           0xffffff00
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_SHIFT          8

/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: MAX_RAVE_CONTEXTS [07:00] */
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_MASK   0x000000ff
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_SHIFT  0

/***************************************************************************
 *MAX_SCDS - Data Transport max number of SCDs supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_SCDS :: reserved0 [31:08] */
#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_MASK                    0xffffff00
#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_SHIFT                   8

/* XPT_BUS_IF :: MAX_SCDS :: MAX_SCDS [07:00] */
#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_MASK                     0x000000ff
#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_SHIFT                    0

#endif /* #ifndef BCHP_XPT_BUS_IF_H__ */

/* End of File */
