/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_pri_arb_control_regs.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:14p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:43:12 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:14p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_PRI_ARB_CONTROL_REGS_H__
#define BCHP_PRI_ARB_CONTROL_REGS_H__

/***************************************************************************
 *PRI_ARB_CONTROL_REGS - PRIMARY_ARB control registers
 ***************************************************************************/
#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0  0x0040cb00 /* Refresh client control for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0 0x0040cb04 /* Write timeout control for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0 0x0040cb08 /* Write timeout status for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0 0x0040cb0c /* Write timeout status clear for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC 0x0040cb10 /* Write timeout bad concentrators */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL   0x0040cb14 /* Performance Monitor Control */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR   0x0040cb18 /* Performance Monitor Clear Counts */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0 0x0040cb1c /* Performance Monitor Events for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0 0x0040cb20 /* Performance Monitor Sum of Latencies for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0 0x0040cb24 /* Performance Monitor Sum of Request Sizes for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0 0x0040cb28 /* Performance Monitor Maximum Latency for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A 0x0040cb2c /* Performance Monitor Client Access bits 19:0 for ddr interface #0 */
#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL     0x0040cb30 /* Master Control */

/***************************************************************************
 *REFRESH_CTL_0 - Refresh client control for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: reserved0 [31:13] */
#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_reserved0_MASK     0xffffe000
#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_reserved0_SHIFT    13

/* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: enable [12:12] */
#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK        0x00001000
#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_SHIFT       12

/* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: period [11:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_period_MASK        0x00000fff
#define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_period_SHIFT       0

/***************************************************************************
 *WR_TIMEOUT_CTL_0 - Write timeout control for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: reserved0 [31:13] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_reserved0_MASK  0xffffe000
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_reserved0_SHIFT 13

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: enable [12:12] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_enable_MASK     0x00001000
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_enable_SHIFT    12

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: period [11:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_period_MASK     0x00000fff
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_period_SHIFT    0

/***************************************************************************
 *WR_TIMEOUT_STS_0 - Write timeout status for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: reserved0 [31:10] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved0_MASK  0xfffffc00
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved0_SHIFT 10

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: long [09:09] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_long_MASK       0x00000200
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_long_SHIFT      9

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: short [08:08] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_short_MASK      0x00000100
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_short_SHIFT     8

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: reserved1 [07:07] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved1_MASK  0x00000080
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved1_SHIFT 7

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: client [06:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_client_MASK     0x0000007f
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_client_SHIFT    0

/***************************************************************************
 *WR_TIMEOUT_CLR_0 - Write timeout status clear for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CLR_0 :: reserved0 [31:01] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_reserved0_MASK  0xfffffffe
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_reserved0_SHIFT 1

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CLR_0 :: clear [00:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_clear_MASK      0x00000001
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_clear_SHIFT     0

/***************************************************************************
 *WR_TIMEOUT_BAD_CONC - Write timeout bad concentrators
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: reserved0 [31:07] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_reserved0_MASK 0xffffff80
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_reserved0_SHIFT 7

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_06 [06:06] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_06_MASK 0x00000040
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_06_SHIFT 6

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_05 [05:05] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_05_MASK 0x00000020
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_05_SHIFT 5

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_04 [04:04] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_04_MASK 0x00000010
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_04_SHIFT 4

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_03 [03:03] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_03_MASK 0x00000008
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_03_SHIFT 3

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_02 [02:02] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_02_MASK 0x00000004
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_02_SHIFT 2

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_01 [01:01] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_01_MASK 0x00000002
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_01_SHIFT 1

/* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_00 [00:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_00_MASK 0x00000001
#define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_00_SHIFT 0

/***************************************************************************
 *PERF_MON_CTL - Performance Monitor Control
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: reserved0 [31:16] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved0_MASK      0xffff0000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved0_SHIFT     16

/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: client_sel [15:08] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_client_sel_MASK     0x0000ff00
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_client_sel_SHIFT    8

/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: reserved1 [07:03] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved1_MASK      0x000000f8
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved1_SHIFT     3

/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: wr_enable [02:02] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_wr_enable_MASK      0x00000004
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_wr_enable_SHIFT     2

/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: rd_enable [01:01] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_rd_enable_MASK      0x00000002
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_rd_enable_SHIFT     1

/* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: enable [00:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_enable_MASK         0x00000001
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_enable_SHIFT        0

/***************************************************************************
 *PERF_MON_CLR - Performance Monitor Clear Counts
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: PERF_MON_CLR :: reserved0 [31:01] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_reserved0_MASK      0xfffffffe
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_reserved0_SHIFT     1

/* PRI_ARB_CONTROL_REGS :: PERF_MON_CLR :: clear [00:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_clear_MASK          0x00000001
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_clear_SHIFT         0

/***************************************************************************
 *PERF_MON_EVENTS_0 - Performance Monitor Events for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: PERF_MON_EVENTS_0 :: count [31:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0_count_MASK     0xffffffff
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0_count_SHIFT    0

/***************************************************************************
 *PERF_MON_SUM_0 - Performance Monitor Sum of Latencies for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: PERF_MON_SUM_0 :: count [31:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0_count_MASK        0xffffffff
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0_count_SHIFT       0

/***************************************************************************
 *PERF_MON_SIZE_SUM_0 - Performance Monitor Sum of Request Sizes for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: PERF_MON_SIZE_SUM_0 :: count [31:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0_count_MASK   0xffffffff
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0_count_SHIFT  0

/***************************************************************************
 *PERF_MON_MAX_0 - Performance Monitor Maximum Latency for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: PERF_MON_MAX_0 :: count [31:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0_count_MASK        0xffffffff
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0_count_SHIFT       0

/***************************************************************************
 *PERF_MON_ACCESS_0A - Performance Monitor Client Access bits 19:0 for ddr interface #0
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: reserved0 [31:20] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_reserved0_MASK 0xfff00000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_reserved0_SHIFT 20

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_19 [19:19] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_19_MASK 0x00080000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_19_SHIFT 19

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_18 [18:18] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_18_MASK 0x00040000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_18_SHIFT 18

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_17 [17:17] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_17_MASK 0x00020000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_17_SHIFT 17

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_16 [16:16] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_16_MASK 0x00010000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_16_SHIFT 16

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_15 [15:15] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_15_MASK 0x00008000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_15_SHIFT 15

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_14 [14:14] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_14_MASK 0x00004000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_14_SHIFT 14

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_13 [13:13] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_13_MASK 0x00002000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_13_SHIFT 13

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_12 [12:12] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_12_MASK 0x00001000
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_12_SHIFT 12

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_11 [11:11] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_11_MASK 0x00000800
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_11_SHIFT 11

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_10 [10:10] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_10_MASK 0x00000400
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_10_SHIFT 10

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_09 [09:09] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_09_MASK 0x00000200
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_09_SHIFT 9

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_08 [08:08] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_08_MASK 0x00000100
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_08_SHIFT 8

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_07 [07:07] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_07_MASK 0x00000080
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_07_SHIFT 7

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_06 [06:06] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_06_MASK 0x00000040
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_06_SHIFT 6

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_05 [05:05] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_05_MASK 0x00000020
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_05_SHIFT 5

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_04 [04:04] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_04_MASK 0x00000010
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_04_SHIFT 4

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_03 [03:03] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_03_MASK 0x00000008
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_03_SHIFT 3

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_02 [02:02] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_02_MASK 0x00000004
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_02_SHIFT 2

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_01 [01:01] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_01_MASK 0x00000002
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_01_SHIFT 1

/* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_00 [00:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_00_MASK 0x00000001
#define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_00_SHIFT 0

/***************************************************************************
 *MASTER_CTL - Master Control
 ***************************************************************************/
/* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: reserved0 [31:01] */
#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_reserved0_MASK        0xfffffffe
#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_reserved0_SHIFT       1

/* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: arb_disable [00:00] */
#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_MASK      0x00000001
#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_SHIFT     0
#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable    0
#define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable   1

#endif /* #ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ */

/* End of File */
