/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_bvnt_intr2.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 7:57p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:43:21 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 7:57p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_BVNT_INTR2_H__
#define BCHP_BVNT_INTR2_H__

/***************************************************************************
 *BVNT_INTR2 - BVN Interrupt Controller Registers
 ***************************************************************************/
#define BCHP_BVNT_INTR2_CPU_STATUS               0x00541200 /* CPU interrupt Status Register */
#define BCHP_BVNT_INTR2_CPU_SET                  0x00541204 /* CPU interrupt Set Register */
#define BCHP_BVNT_INTR2_CPU_CLEAR                0x00541208 /* CPU interrupt Clear Register */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS          0x0054120c /* CPU interrupt Mask Status Register */
#define BCHP_BVNT_INTR2_CPU_MASK_SET             0x00541210 /* CPU interrupt Mask Set Register */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR           0x00541214 /* CPU interrupt Mask Clear Register */
#define BCHP_BVNT_INTR2_PCI_STATUS               0x00541218 /* PCI interrupt Status Register */
#define BCHP_BVNT_INTR2_PCI_SET                  0x0054121c /* PCI interrupt Set Register */
#define BCHP_BVNT_INTR2_PCI_CLEAR                0x00541220 /* PCI interrupt Clear Register */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS          0x00541224 /* PCI interrupt Mask Status Register */
#define BCHP_BVNT_INTR2_PCI_MASK_SET             0x00541228 /* PCI interrupt Mask Set Register */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR           0x0054122c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* BVNT_INTR2 :: CPU_STATUS :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_CPU_STATUS_reserved0_MASK                  0xfffffe00
#define BCHP_BVNT_INTR2_CPU_STATUS_reserved0_SHIFT                 9

/* BVNT_INTR2 :: CPU_STATUS :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_CPU_STATUS_BOP_EOF_INTR_MASK               0x00000100
#define BCHP_BVNT_INTR2_CPU_STATUS_BOP_EOF_INTR_SHIFT              8

/* BVNT_INTR2 :: CPU_STATUS :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_CPU_STATUS_BVN_EOF_INTR_MASK               0x00000080
#define BCHP_BVNT_INTR2_CPU_STATUS_BVN_EOF_INTR_SHIFT              7

/* BVNT_INTR2 :: CPU_STATUS :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_CPU_STATUS_METADMA_INTR_MASK               0x00000040
#define BCHP_BVNT_INTR2_CPU_STATUS_METADMA_INTR_SHIFT              6

/* BVNT_INTR2 :: CPU_STATUS :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_CPU_STATUS_RXDMA3_INTR_MASK                0x00000020
#define BCHP_BVNT_INTR2_CPU_STATUS_RXDMA3_INTR_SHIFT               5

/* BVNT_INTR2 :: CPU_STATUS :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_CPU_STATUS_TXDMA_INTR_MASK                 0x00000010
#define BCHP_BVNT_INTR2_CPU_STATUS_TXDMA_INTR_SHIFT                4

/* BVNT_INTR2 :: CPU_STATUS :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_CPU_STATUS_SCL_INTR_MASK                   0x00000008
#define BCHP_BVNT_INTR2_CPU_STATUS_SCL_INTR_SHIFT                  3

/* BVNT_INTR2 :: CPU_STATUS :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_CPU_STATUS_DNR_INTR_MASK                   0x00000004
#define BCHP_BVNT_INTR2_CPU_STATUS_DNR_INTR_SHIFT                  2

/* BVNT_INTR2 :: CPU_STATUS :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_CPU_STATUS_EOF_INTR_MASK                   0x00000002
#define BCHP_BVNT_INTR2_CPU_STATUS_EOF_INTR_SHIFT                  1

/* BVNT_INTR2 :: CPU_STATUS :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_CPU_STATUS_MFD_INTR_MASK                   0x00000001
#define BCHP_BVNT_INTR2_CPU_STATUS_MFD_INTR_SHIFT                  0

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* BVNT_INTR2 :: CPU_SET :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_CPU_SET_reserved0_MASK                     0xfffffe00
#define BCHP_BVNT_INTR2_CPU_SET_reserved0_SHIFT                    9

/* BVNT_INTR2 :: CPU_SET :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_CPU_SET_BOP_EOF_INTR_MASK                  0x00000100
#define BCHP_BVNT_INTR2_CPU_SET_BOP_EOF_INTR_SHIFT                 8

/* BVNT_INTR2 :: CPU_SET :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_CPU_SET_BVN_EOF_INTR_MASK                  0x00000080
#define BCHP_BVNT_INTR2_CPU_SET_BVN_EOF_INTR_SHIFT                 7

/* BVNT_INTR2 :: CPU_SET :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_CPU_SET_METADMA_INTR_MASK                  0x00000040
#define BCHP_BVNT_INTR2_CPU_SET_METADMA_INTR_SHIFT                 6

/* BVNT_INTR2 :: CPU_SET :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_CPU_SET_RXDMA3_INTR_MASK                   0x00000020
#define BCHP_BVNT_INTR2_CPU_SET_RXDMA3_INTR_SHIFT                  5

/* BVNT_INTR2 :: CPU_SET :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_CPU_SET_TXDMA_INTR_MASK                    0x00000010
#define BCHP_BVNT_INTR2_CPU_SET_TXDMA_INTR_SHIFT                   4

/* BVNT_INTR2 :: CPU_SET :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_CPU_SET_SCL_INTR_MASK                      0x00000008
#define BCHP_BVNT_INTR2_CPU_SET_SCL_INTR_SHIFT                     3

/* BVNT_INTR2 :: CPU_SET :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_CPU_SET_DNR_INTR_MASK                      0x00000004
#define BCHP_BVNT_INTR2_CPU_SET_DNR_INTR_SHIFT                     2

/* BVNT_INTR2 :: CPU_SET :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_CPU_SET_EOF_INTR_MASK                      0x00000002
#define BCHP_BVNT_INTR2_CPU_SET_EOF_INTR_SHIFT                     1

/* BVNT_INTR2 :: CPU_SET :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_CPU_SET_MFD_INTR_MASK                      0x00000001
#define BCHP_BVNT_INTR2_CPU_SET_MFD_INTR_SHIFT                     0

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* BVNT_INTR2 :: CPU_CLEAR :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_reserved0_MASK                   0xfffffe00
#define BCHP_BVNT_INTR2_CPU_CLEAR_reserved0_SHIFT                  9

/* BVNT_INTR2 :: CPU_CLEAR :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_BOP_EOF_INTR_MASK                0x00000100
#define BCHP_BVNT_INTR2_CPU_CLEAR_BOP_EOF_INTR_SHIFT               8

/* BVNT_INTR2 :: CPU_CLEAR :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_BVN_EOF_INTR_MASK                0x00000080
#define BCHP_BVNT_INTR2_CPU_CLEAR_BVN_EOF_INTR_SHIFT               7

/* BVNT_INTR2 :: CPU_CLEAR :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_METADMA_INTR_MASK                0x00000040
#define BCHP_BVNT_INTR2_CPU_CLEAR_METADMA_INTR_SHIFT               6

/* BVNT_INTR2 :: CPU_CLEAR :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_RXDMA3_INTR_MASK                 0x00000020
#define BCHP_BVNT_INTR2_CPU_CLEAR_RXDMA3_INTR_SHIFT                5

/* BVNT_INTR2 :: CPU_CLEAR :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_TXDMA_INTR_MASK                  0x00000010
#define BCHP_BVNT_INTR2_CPU_CLEAR_TXDMA_INTR_SHIFT                 4

/* BVNT_INTR2 :: CPU_CLEAR :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_SCL_INTR_MASK                    0x00000008
#define BCHP_BVNT_INTR2_CPU_CLEAR_SCL_INTR_SHIFT                   3

/* BVNT_INTR2 :: CPU_CLEAR :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_DNR_INTR_MASK                    0x00000004
#define BCHP_BVNT_INTR2_CPU_CLEAR_DNR_INTR_SHIFT                   2

/* BVNT_INTR2 :: CPU_CLEAR :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_EOF_INTR_MASK                    0x00000002
#define BCHP_BVNT_INTR2_CPU_CLEAR_EOF_INTR_SHIFT                   1

/* BVNT_INTR2 :: CPU_CLEAR :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_CPU_CLEAR_MFD_INTR_MASK                    0x00000001
#define BCHP_BVNT_INTR2_CPU_CLEAR_MFD_INTR_SHIFT                   0

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* BVNT_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_reserved0_MASK             0xfffffe00
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_reserved0_SHIFT            9

/* BVNT_INTR2 :: CPU_MASK_STATUS :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BOP_EOF_INTR_MASK          0x00000100
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BOP_EOF_INTR_SHIFT         8

/* BVNT_INTR2 :: CPU_MASK_STATUS :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BVN_EOF_INTR_MASK          0x00000080
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BVN_EOF_INTR_SHIFT         7

/* BVNT_INTR2 :: CPU_MASK_STATUS :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_METADMA_INTR_MASK          0x00000040
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_METADMA_INTR_SHIFT         6

/* BVNT_INTR2 :: CPU_MASK_STATUS :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_RXDMA3_INTR_MASK           0x00000020
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_RXDMA3_INTR_SHIFT          5

/* BVNT_INTR2 :: CPU_MASK_STATUS :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_TXDMA_INTR_MASK            0x00000010
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_TXDMA_INTR_SHIFT           4

/* BVNT_INTR2 :: CPU_MASK_STATUS :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_SCL_INTR_MASK              0x00000008
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_SCL_INTR_SHIFT             3

/* BVNT_INTR2 :: CPU_MASK_STATUS :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_DNR_INTR_MASK              0x00000004
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_DNR_INTR_SHIFT             2

/* BVNT_INTR2 :: CPU_MASK_STATUS :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_EOF_INTR_MASK              0x00000002
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_EOF_INTR_SHIFT             1

/* BVNT_INTR2 :: CPU_MASK_STATUS :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_MFD_INTR_MASK              0x00000001
#define BCHP_BVNT_INTR2_CPU_MASK_STATUS_MFD_INTR_SHIFT             0

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* BVNT_INTR2 :: CPU_MASK_SET :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_reserved0_MASK                0xfffffe00
#define BCHP_BVNT_INTR2_CPU_MASK_SET_reserved0_SHIFT               9

/* BVNT_INTR2 :: CPU_MASK_SET :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_BOP_EOF_INTR_MASK             0x00000100
#define BCHP_BVNT_INTR2_CPU_MASK_SET_BOP_EOF_INTR_SHIFT            8

/* BVNT_INTR2 :: CPU_MASK_SET :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_BVN_EOF_INTR_MASK             0x00000080
#define BCHP_BVNT_INTR2_CPU_MASK_SET_BVN_EOF_INTR_SHIFT            7

/* BVNT_INTR2 :: CPU_MASK_SET :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_METADMA_INTR_MASK             0x00000040
#define BCHP_BVNT_INTR2_CPU_MASK_SET_METADMA_INTR_SHIFT            6

/* BVNT_INTR2 :: CPU_MASK_SET :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_RXDMA3_INTR_MASK              0x00000020
#define BCHP_BVNT_INTR2_CPU_MASK_SET_RXDMA3_INTR_SHIFT             5

/* BVNT_INTR2 :: CPU_MASK_SET :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_TXDMA_INTR_MASK               0x00000010
#define BCHP_BVNT_INTR2_CPU_MASK_SET_TXDMA_INTR_SHIFT              4

/* BVNT_INTR2 :: CPU_MASK_SET :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_SCL_INTR_MASK                 0x00000008
#define BCHP_BVNT_INTR2_CPU_MASK_SET_SCL_INTR_SHIFT                3

/* BVNT_INTR2 :: CPU_MASK_SET :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_DNR_INTR_MASK                 0x00000004
#define BCHP_BVNT_INTR2_CPU_MASK_SET_DNR_INTR_SHIFT                2

/* BVNT_INTR2 :: CPU_MASK_SET :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_EOF_INTR_MASK                 0x00000002
#define BCHP_BVNT_INTR2_CPU_MASK_SET_EOF_INTR_SHIFT                1

/* BVNT_INTR2 :: CPU_MASK_SET :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_CPU_MASK_SET_MFD_INTR_MASK                 0x00000001
#define BCHP_BVNT_INTR2_CPU_MASK_SET_MFD_INTR_SHIFT                0

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* BVNT_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_reserved0_MASK              0xfffffe00
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT             9

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BOP_EOF_INTR_MASK           0x00000100
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BOP_EOF_INTR_SHIFT          8

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BVN_EOF_INTR_MASK           0x00000080
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BVN_EOF_INTR_SHIFT          7

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_METADMA_INTR_MASK           0x00000040
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_METADMA_INTR_SHIFT          6

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_RXDMA3_INTR_MASK            0x00000020
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_RXDMA3_INTR_SHIFT           5

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_TXDMA_INTR_MASK             0x00000010
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_TXDMA_INTR_SHIFT            4

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_SCL_INTR_MASK               0x00000008
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_SCL_INTR_SHIFT              3

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_DNR_INTR_MASK               0x00000004
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_DNR_INTR_SHIFT              2

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_EOF_INTR_MASK               0x00000002
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_EOF_INTR_SHIFT              1

/* BVNT_INTR2 :: CPU_MASK_CLEAR :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_MFD_INTR_MASK               0x00000001
#define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_MFD_INTR_SHIFT              0

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* BVNT_INTR2 :: PCI_STATUS :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_PCI_STATUS_reserved0_MASK                  0xfffffe00
#define BCHP_BVNT_INTR2_PCI_STATUS_reserved0_SHIFT                 9

/* BVNT_INTR2 :: PCI_STATUS :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_PCI_STATUS_BOP_EOF_INTR_MASK               0x00000100
#define BCHP_BVNT_INTR2_PCI_STATUS_BOP_EOF_INTR_SHIFT              8

/* BVNT_INTR2 :: PCI_STATUS :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_PCI_STATUS_BVN_EOF_INTR_MASK               0x00000080
#define BCHP_BVNT_INTR2_PCI_STATUS_BVN_EOF_INTR_SHIFT              7

/* BVNT_INTR2 :: PCI_STATUS :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_PCI_STATUS_METADMA_INTR_MASK               0x00000040
#define BCHP_BVNT_INTR2_PCI_STATUS_METADMA_INTR_SHIFT              6

/* BVNT_INTR2 :: PCI_STATUS :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_PCI_STATUS_RXDMA3_INTR_MASK                0x00000020
#define BCHP_BVNT_INTR2_PCI_STATUS_RXDMA3_INTR_SHIFT               5

/* BVNT_INTR2 :: PCI_STATUS :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_PCI_STATUS_TXDMA_INTR_MASK                 0x00000010
#define BCHP_BVNT_INTR2_PCI_STATUS_TXDMA_INTR_SHIFT                4

/* BVNT_INTR2 :: PCI_STATUS :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_PCI_STATUS_SCL_INTR_MASK                   0x00000008
#define BCHP_BVNT_INTR2_PCI_STATUS_SCL_INTR_SHIFT                  3

/* BVNT_INTR2 :: PCI_STATUS :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_PCI_STATUS_DNR_INTR_MASK                   0x00000004
#define BCHP_BVNT_INTR2_PCI_STATUS_DNR_INTR_SHIFT                  2

/* BVNT_INTR2 :: PCI_STATUS :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_PCI_STATUS_EOF_INTR_MASK                   0x00000002
#define BCHP_BVNT_INTR2_PCI_STATUS_EOF_INTR_SHIFT                  1

/* BVNT_INTR2 :: PCI_STATUS :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_PCI_STATUS_MFD_INTR_MASK                   0x00000001
#define BCHP_BVNT_INTR2_PCI_STATUS_MFD_INTR_SHIFT                  0

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* BVNT_INTR2 :: PCI_SET :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_PCI_SET_reserved0_MASK                     0xfffffe00
#define BCHP_BVNT_INTR2_PCI_SET_reserved0_SHIFT                    9

/* BVNT_INTR2 :: PCI_SET :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_PCI_SET_BOP_EOF_INTR_MASK                  0x00000100
#define BCHP_BVNT_INTR2_PCI_SET_BOP_EOF_INTR_SHIFT                 8

/* BVNT_INTR2 :: PCI_SET :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_PCI_SET_BVN_EOF_INTR_MASK                  0x00000080
#define BCHP_BVNT_INTR2_PCI_SET_BVN_EOF_INTR_SHIFT                 7

/* BVNT_INTR2 :: PCI_SET :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_PCI_SET_METADMA_INTR_MASK                  0x00000040
#define BCHP_BVNT_INTR2_PCI_SET_METADMA_INTR_SHIFT                 6

/* BVNT_INTR2 :: PCI_SET :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_PCI_SET_RXDMA3_INTR_MASK                   0x00000020
#define BCHP_BVNT_INTR2_PCI_SET_RXDMA3_INTR_SHIFT                  5

/* BVNT_INTR2 :: PCI_SET :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_PCI_SET_TXDMA_INTR_MASK                    0x00000010
#define BCHP_BVNT_INTR2_PCI_SET_TXDMA_INTR_SHIFT                   4

/* BVNT_INTR2 :: PCI_SET :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_PCI_SET_SCL_INTR_MASK                      0x00000008
#define BCHP_BVNT_INTR2_PCI_SET_SCL_INTR_SHIFT                     3

/* BVNT_INTR2 :: PCI_SET :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_PCI_SET_DNR_INTR_MASK                      0x00000004
#define BCHP_BVNT_INTR2_PCI_SET_DNR_INTR_SHIFT                     2

/* BVNT_INTR2 :: PCI_SET :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_PCI_SET_EOF_INTR_MASK                      0x00000002
#define BCHP_BVNT_INTR2_PCI_SET_EOF_INTR_SHIFT                     1

/* BVNT_INTR2 :: PCI_SET :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_PCI_SET_MFD_INTR_MASK                      0x00000001
#define BCHP_BVNT_INTR2_PCI_SET_MFD_INTR_SHIFT                     0

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* BVNT_INTR2 :: PCI_CLEAR :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_reserved0_MASK                   0xfffffe00
#define BCHP_BVNT_INTR2_PCI_CLEAR_reserved0_SHIFT                  9

/* BVNT_INTR2 :: PCI_CLEAR :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_BOP_EOF_INTR_MASK                0x00000100
#define BCHP_BVNT_INTR2_PCI_CLEAR_BOP_EOF_INTR_SHIFT               8

/* BVNT_INTR2 :: PCI_CLEAR :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_BVN_EOF_INTR_MASK                0x00000080
#define BCHP_BVNT_INTR2_PCI_CLEAR_BVN_EOF_INTR_SHIFT               7

/* BVNT_INTR2 :: PCI_CLEAR :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_METADMA_INTR_MASK                0x00000040
#define BCHP_BVNT_INTR2_PCI_CLEAR_METADMA_INTR_SHIFT               6

/* BVNT_INTR2 :: PCI_CLEAR :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_RXDMA3_INTR_MASK                 0x00000020
#define BCHP_BVNT_INTR2_PCI_CLEAR_RXDMA3_INTR_SHIFT                5

/* BVNT_INTR2 :: PCI_CLEAR :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_TXDMA_INTR_MASK                  0x00000010
#define BCHP_BVNT_INTR2_PCI_CLEAR_TXDMA_INTR_SHIFT                 4

/* BVNT_INTR2 :: PCI_CLEAR :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_SCL_INTR_MASK                    0x00000008
#define BCHP_BVNT_INTR2_PCI_CLEAR_SCL_INTR_SHIFT                   3

/* BVNT_INTR2 :: PCI_CLEAR :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_DNR_INTR_MASK                    0x00000004
#define BCHP_BVNT_INTR2_PCI_CLEAR_DNR_INTR_SHIFT                   2

/* BVNT_INTR2 :: PCI_CLEAR :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_EOF_INTR_MASK                    0x00000002
#define BCHP_BVNT_INTR2_PCI_CLEAR_EOF_INTR_SHIFT                   1

/* BVNT_INTR2 :: PCI_CLEAR :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_PCI_CLEAR_MFD_INTR_MASK                    0x00000001
#define BCHP_BVNT_INTR2_PCI_CLEAR_MFD_INTR_SHIFT                   0

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* BVNT_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_reserved0_MASK             0xfffffe00
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_reserved0_SHIFT            9

/* BVNT_INTR2 :: PCI_MASK_STATUS :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BOP_EOF_INTR_MASK          0x00000100
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BOP_EOF_INTR_SHIFT         8

/* BVNT_INTR2 :: PCI_MASK_STATUS :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BVN_EOF_INTR_MASK          0x00000080
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BVN_EOF_INTR_SHIFT         7

/* BVNT_INTR2 :: PCI_MASK_STATUS :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_METADMA_INTR_MASK          0x00000040
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_METADMA_INTR_SHIFT         6

/* BVNT_INTR2 :: PCI_MASK_STATUS :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_RXDMA3_INTR_MASK           0x00000020
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_RXDMA3_INTR_SHIFT          5

/* BVNT_INTR2 :: PCI_MASK_STATUS :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_TXDMA_INTR_MASK            0x00000010
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_TXDMA_INTR_SHIFT           4

/* BVNT_INTR2 :: PCI_MASK_STATUS :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_SCL_INTR_MASK              0x00000008
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_SCL_INTR_SHIFT             3

/* BVNT_INTR2 :: PCI_MASK_STATUS :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_DNR_INTR_MASK              0x00000004
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_DNR_INTR_SHIFT             2

/* BVNT_INTR2 :: PCI_MASK_STATUS :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_EOF_INTR_MASK              0x00000002
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_EOF_INTR_SHIFT             1

/* BVNT_INTR2 :: PCI_MASK_STATUS :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_MFD_INTR_MASK              0x00000001
#define BCHP_BVNT_INTR2_PCI_MASK_STATUS_MFD_INTR_SHIFT             0

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* BVNT_INTR2 :: PCI_MASK_SET :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_reserved0_MASK                0xfffffe00
#define BCHP_BVNT_INTR2_PCI_MASK_SET_reserved0_SHIFT               9

/* BVNT_INTR2 :: PCI_MASK_SET :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_BOP_EOF_INTR_MASK             0x00000100
#define BCHP_BVNT_INTR2_PCI_MASK_SET_BOP_EOF_INTR_SHIFT            8

/* BVNT_INTR2 :: PCI_MASK_SET :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_BVN_EOF_INTR_MASK             0x00000080
#define BCHP_BVNT_INTR2_PCI_MASK_SET_BVN_EOF_INTR_SHIFT            7

/* BVNT_INTR2 :: PCI_MASK_SET :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_METADMA_INTR_MASK             0x00000040
#define BCHP_BVNT_INTR2_PCI_MASK_SET_METADMA_INTR_SHIFT            6

/* BVNT_INTR2 :: PCI_MASK_SET :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_RXDMA3_INTR_MASK              0x00000020
#define BCHP_BVNT_INTR2_PCI_MASK_SET_RXDMA3_INTR_SHIFT             5

/* BVNT_INTR2 :: PCI_MASK_SET :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_TXDMA_INTR_MASK               0x00000010
#define BCHP_BVNT_INTR2_PCI_MASK_SET_TXDMA_INTR_SHIFT              4

/* BVNT_INTR2 :: PCI_MASK_SET :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_SCL_INTR_MASK                 0x00000008
#define BCHP_BVNT_INTR2_PCI_MASK_SET_SCL_INTR_SHIFT                3

/* BVNT_INTR2 :: PCI_MASK_SET :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_DNR_INTR_MASK                 0x00000004
#define BCHP_BVNT_INTR2_PCI_MASK_SET_DNR_INTR_SHIFT                2

/* BVNT_INTR2 :: PCI_MASK_SET :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_EOF_INTR_MASK                 0x00000002
#define BCHP_BVNT_INTR2_PCI_MASK_SET_EOF_INTR_SHIFT                1

/* BVNT_INTR2 :: PCI_MASK_SET :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_PCI_MASK_SET_MFD_INTR_MASK                 0x00000001
#define BCHP_BVNT_INTR2_PCI_MASK_SET_MFD_INTR_SHIFT                0

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* BVNT_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:09] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_reserved0_MASK              0xfffffe00
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT             9

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: BOP_EOF_INTR [08:08] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BOP_EOF_INTR_MASK           0x00000100
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BOP_EOF_INTR_SHIFT          8

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: BVN_EOF_INTR [07:07] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BVN_EOF_INTR_MASK           0x00000080
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BVN_EOF_INTR_SHIFT          7

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: METADMA_INTR [06:06] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_METADMA_INTR_MASK           0x00000040
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_METADMA_INTR_SHIFT          6

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: RXDMA3_INTR [05:05] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_RXDMA3_INTR_MASK            0x00000020
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_RXDMA3_INTR_SHIFT           5

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: TXDMA_INTR [04:04] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_TXDMA_INTR_MASK             0x00000010
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_TXDMA_INTR_SHIFT            4

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: SCL_INTR [03:03] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_SCL_INTR_MASK               0x00000008
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_SCL_INTR_SHIFT              3

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: DNR_INTR [02:02] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_DNR_INTR_MASK               0x00000004
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_DNR_INTR_SHIFT              2

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: EOF_INTR [01:01] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_EOF_INTR_MASK               0x00000002
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_EOF_INTR_SHIFT              1

/* BVNT_INTR2 :: PCI_MASK_CLEAR :: MFD_INTR [00:00] */
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_MFD_INTR_MASK               0x00000001
#define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_MFD_INTR_SHIFT              0

#endif /* #ifndef BCHP_BVNT_INTR2_H__ */

/* End of File */
