/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_cce_rgr_bridge.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 7:58p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:58 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 7:58p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_CCE_RGR_BRIDGE_H__
#define BCHP_CCE_RGR_BRIDGE_H__

/***************************************************************************
 *CCE_RGR_BRIDGE - CCE RGR-bridge related registers
 ***************************************************************************/
#define BCHP_CCE_RGR_BRIDGE_REVISION             0x005033e0 /* RGR Bridge Revision */
#define BCHP_CCE_RGR_BRIDGE_CTRL                 0x005033e4 /* RGR Bridge Control Register */
#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER           0x005033e8 /* RGR Bridge RBUS Timer Register */
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0     0x005033ec /* RGR Bridge Software Reset 0 Register */
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1     0x005033f0 /* RGR Bridge Software Reset 1 Register */

/***************************************************************************
 *REVISION - RGR Bridge Revision
 ***************************************************************************/
/* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */
#define BCHP_CCE_RGR_BRIDGE_REVISION_reserved0_MASK                0xffff0000
#define BCHP_CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT               16

/* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */
#define BCHP_CCE_RGR_BRIDGE_REVISION_MAJOR_MASK                    0x0000ff00
#define BCHP_CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT                   8

/* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */
#define BCHP_CCE_RGR_BRIDGE_REVISION_MINOR_MASK                    0x000000ff
#define BCHP_CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT                   0

/***************************************************************************
 *CTRL - RGR Bridge Control Register
 ***************************************************************************/
/* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */
#define BCHP_CCE_RGR_BRIDGE_CTRL_reserved0_MASK                    0xfffffffc
#define BCHP_CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT                   2

/* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */
#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK              0x00000002
#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT             1
#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE      0
#define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE       1

/* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */
#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK              0x00000001
#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT             0
#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE      0
#define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE       1

/***************************************************************************
 *RBUS_TIMER - RGR Bridge RBUS Timer Register
 ***************************************************************************/
/* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */
#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK              0xffff0000
#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT             16

/* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */
#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK            0x0000ffff
#define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT           0

/***************************************************************************
 *SPARE_SW_RESET_0 - RGR Bridge Software Reset 0 Register
 ***************************************************************************/
/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK        0xfffffffe
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT       1

/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK   0x00000001
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT  0
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1

/***************************************************************************
 *SPARE_SW_RESET_1 - RGR Bridge Software Reset 1 Register
 ***************************************************************************/
/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK        0xfffffffe
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT       1

/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK   0x00000001
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT  0
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0
#define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1

#endif /* #ifndef BCHP_CCE_RGR_BRIDGE_H__ */

/* End of File */
