/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_pri_rts_l2_regs_1.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:17p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:23 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:17p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_PRI_RTS_L2_REGS_1_H__
#define BCHP_PRI_RTS_L2_REGS_1_H__

/***************************************************************************
 *PRI_RTS_L2_REGS_1 - PRIMARY_ARB_CLIENTS L2 (Mips) rts interrupt controller 1 registers
 ***************************************************************************/
#define BCHP_PRI_RTS_L2_REGS_1_CPU_STATUS        0x0040c4c0 /* CPU interrupt Status Register */
#define BCHP_PRI_RTS_L2_REGS_1_CPU_SET           0x0040c4c4 /* CPU interrupt Set Register */
#define BCHP_PRI_RTS_L2_REGS_1_CPU_CLEAR         0x0040c4c8 /* CPU interrupt Clear Register */
#define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_STATUS   0x0040c4cc /* CPU interrupt Mask Status Register */
#define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_SET      0x0040c4d0 /* CPU interrupt Mask Set Register */
#define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_CLEAR    0x0040c4d4 /* CPU interrupt Mask Clear Register */
#define BCHP_PRI_RTS_L2_REGS_1_PCI_STATUS        0x0040c4d8 /* PCI interrupt Status Register */
#define BCHP_PRI_RTS_L2_REGS_1_PCI_SET           0x0040c4dc /* PCI interrupt Set Register */
#define BCHP_PRI_RTS_L2_REGS_1_PCI_CLEAR         0x0040c4e0 /* PCI interrupt Clear Register */
#define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_STATUS   0x0040c4e4 /* PCI interrupt Mask Status Register */
#define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_SET      0x0040c4e8 /* PCI interrupt Mask Set Register */
#define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_CLEAR    0x0040c4ec /* PCI interrupt Mask Clear Register */

#endif /* #ifndef BCHP_PRI_RTS_L2_REGS_1_H__ */

/* End of File */
