/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_wrap_misc_intr2.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:23p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:43:21 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:23p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_WRAP_MISC_INTR2_H__
#define BCHP_WRAP_MISC_INTR2_H__

/***************************************************************************
 *WRAP_MISC_INTR2 - MISC block Level 2 Interrupt Controller
 ***************************************************************************/
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS          0x000f2000 /* CPU interrupt Status Register */
#define BCHP_WRAP_MISC_INTR2_CPU_SET             0x000f2004 /* CPU interrupt Set Register */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR           0x000f2008 /* CPU interrupt Clear Register */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS     0x000f200c /* CPU interrupt Mask Status Register */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET        0x000f2010 /* CPU interrupt Mask Set Register */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR      0x000f2014 /* CPU interrupt Mask Clear Register */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS          0x000f2018 /* PCI interrupt Status Register */
#define BCHP_WRAP_MISC_INTR2_PCI_SET             0x000f201c /* PCI interrupt Set Register */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR           0x000f2020 /* PCI interrupt Clear Register */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS     0x000f2024 /* PCI interrupt Mask Status Register */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET        0x000f2028 /* PCI interrupt Mask Set Register */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR      0x000f202c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: CPU_STATUS :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_reserved0_MASK             0xff000000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_reserved0_SHIFT            24

/* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_FAIL_INTR [23:23] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_MASK    0x00800000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT   23

/* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_DONE_INTR [22:22] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_MASK    0x00400000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT   22

/* WRAP_MISC_INTR2 :: CPU_STATUS :: PREMATURE_ARM_REQ_INTR [21:21] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PREMATURE_ARM_REQ_INTR_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PREMATURE_ARM_REQ_INTR_SHIFT 21

/* WRAP_MISC_INTR2 :: CPU_STATUS :: BAD_STARCH_CFG_INTR [20:20] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BAD_STARCH_CFG_INTR_MASK   0x00100000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BAD_STARCH_CFG_INTR_SHIFT  20

/* WRAP_MISC_INTR2 :: CPU_STATUS :: SCRM_KEY_DONE_INTR [19:19] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_MASK    0x00080000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT   19

/* WRAP_MISC_INTR2 :: CPU_STATUS :: BORCH_ERROR_INTR [18:18] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BORCH_ERROR_INTR_MASK      0x00040000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BORCH_ERROR_INTR_SHIFT     18

/* WRAP_MISC_INTR2 :: CPU_STATUS :: GR_BRIDGE_ERROR_INTR [17:17] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_GR_BRIDGE_ERROR_INTR_MASK  0x00020000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_GR_BRIDGE_ERROR_INTR_SHIFT 17

/* WRAP_MISC_INTR2 :: CPU_STATUS :: MEM_DMA_INTR [16:16] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_MEM_DMA_INTR_MASK          0x00010000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_MEM_DMA_INTR_SHIFT         16

/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX4_INTR [15:15] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX4_INTR_MASK        0x00008000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX4_INTR_SHIFT       15

/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX3_INTR [14:14] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX3_INTR_MASK        0x00004000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX3_INTR_SHIFT       14

/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX2_INTR [13:13] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX2_INTR_MASK        0x00002000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX2_INTR_SHIFT       13

/* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX1_INTR [12:12] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX1_INTR_MASK        0x00001000
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX1_INTR_SHIFT       12

/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX4_INTR [11:11] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX4_INTR_MASK        0x00000800
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX4_INTR_SHIFT       11

/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX3_INTR [10:10] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX3_INTR_MASK        0x00000400
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX3_INTR_SHIFT       10

/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX2_INTR [09:09] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX2_INTR_MASK        0x00000200
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX2_INTR_SHIFT       9

/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX1_INTR [08:08] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX1_INTR_MASK        0x00000100
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX1_INTR_SHIFT       8

/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL2_INTR [07:07] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL2_INTR_MASK      0x00000080
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL2_INTR_SHIFT     7

/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL1_INTR [06:06] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL1_INTR_MASK      0x00000040
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL1_INTR_SHIFT     6

/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL0_INTR [05:05] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL0_INTR_MASK      0x00000020
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL0_INTR_SHIFT     5

/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_ERR_INTR [04:04] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_MASK        0x00000010
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT       4

/* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_MEM_DMA0_DONE [03:03] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_MEM_DMA0_DONE_MASK   0x00000008
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_MEM_DMA0_DONE_SHIFT  3

/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_INTR [02:02] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_INTR_MASK         0x00000004
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_INTR_SHIFT        2

/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_RCV_INTR [01:01] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_RCV_INTR_MASK     0x00000002
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_RCV_INTR_SHIFT    1

/* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_XMIT_INTR [00:00] */
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_XMIT_INTR_MASK    0x00000001
#define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_XMIT_INTR_SHIFT   0

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: CPU_SET :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_reserved0_MASK                0xff000000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_reserved0_SHIFT               24

/* WRAP_MISC_INTR2 :: CPU_SET :: BOOT_VER_FAIL_INTR [23:23] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_FAIL_INTR_MASK       0x00800000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_FAIL_INTR_SHIFT      23

/* WRAP_MISC_INTR2 :: CPU_SET :: BOOT_VER_DONE_INTR [22:22] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_DONE_INTR_MASK       0x00400000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_DONE_INTR_SHIFT      22

/* WRAP_MISC_INTR2 :: CPU_SET :: PREMATURE_ARM_REQ_INTR [21:21] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PREMATURE_ARM_REQ_INTR_MASK   0x00200000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PREMATURE_ARM_REQ_INTR_SHIFT  21

/* WRAP_MISC_INTR2 :: CPU_SET :: BAD_STARCH_CFG_INTR [20:20] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BAD_STARCH_CFG_INTR_MASK      0x00100000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BAD_STARCH_CFG_INTR_SHIFT     20

/* WRAP_MISC_INTR2 :: CPU_SET :: SCRM_KEY_DONE_INTR [19:19] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SCRM_KEY_DONE_INTR_MASK       0x00080000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SCRM_KEY_DONE_INTR_SHIFT      19

/* WRAP_MISC_INTR2 :: CPU_SET :: BORCH_ERROR_INTR [18:18] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BORCH_ERROR_INTR_MASK         0x00040000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_BORCH_ERROR_INTR_SHIFT        18

/* WRAP_MISC_INTR2 :: CPU_SET :: GR_BRIDGE_ERROR_INTR [17:17] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_GR_BRIDGE_ERROR_INTR_MASK     0x00020000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_GR_BRIDGE_ERROR_INTR_SHIFT    17

/* WRAP_MISC_INTR2 :: CPU_SET :: MEM_DMA_INTR [16:16] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_MEM_DMA_INTR_MASK             0x00010000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_MEM_DMA_INTR_SHIFT            16

/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX4_INTR [15:15] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX4_INTR_MASK           0x00008000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX4_INTR_SHIFT          15

/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX3_INTR [14:14] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX3_INTR_MASK           0x00004000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX3_INTR_SHIFT          14

/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX2_INTR [13:13] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX2_INTR_MASK           0x00002000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX2_INTR_SHIFT          13

/* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX1_INTR [12:12] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX1_INTR_MASK           0x00001000
#define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX1_INTR_SHIFT          12

/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX4_INTR [11:11] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX4_INTR_MASK           0x00000800
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX4_INTR_SHIFT          11

/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX3_INTR [10:10] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX3_INTR_MASK           0x00000400
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX3_INTR_SHIFT          10

/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX2_INTR [09:09] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX2_INTR_MASK           0x00000200
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX2_INTR_SHIFT          9

/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX1_INTR [08:08] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX1_INTR_MASK           0x00000100
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX1_INTR_SHIFT          8

/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL2_INTR [07:07] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL2_INTR_MASK         0x00000080
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL2_INTR_SHIFT        7

/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL1_INTR [06:06] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL1_INTR_MASK         0x00000040
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL1_INTR_SHIFT        6

/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL0_INTR [05:05] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL0_INTR_MASK         0x00000020
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL0_INTR_SHIFT        5

/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_ERR_INTR [04:04] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_ERR_INTR_MASK           0x00000010
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_ERR_INTR_SHIFT          4

/* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_MEM_DMA0_DONE [03:03] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_MEM_DMA0_DONE_MASK      0x00000008
#define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_MEM_DMA0_DONE_SHIFT     3

/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_INTR [02:02] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_INTR_MASK            0x00000004
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_INTR_SHIFT           2

/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_RCV_INTR [01:01] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_RCV_INTR_MASK        0x00000002
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_RCV_INTR_SHIFT       1

/* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_XMIT_INTR [00:00] */
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_XMIT_INTR_MASK       0x00000001
#define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_XMIT_INTR_SHIFT      0

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: CPU_CLEAR :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_reserved0_MASK              0xff000000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_reserved0_SHIFT             24

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BOOT_VER_FAIL_INTR [23:23] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_FAIL_INTR_MASK     0x00800000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_FAIL_INTR_SHIFT    23

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BOOT_VER_DONE_INTR [22:22] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_DONE_INTR_MASK     0x00400000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_DONE_INTR_SHIFT    22

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PREMATURE_ARM_REQ_INTR [21:21] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PREMATURE_ARM_REQ_INTR_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PREMATURE_ARM_REQ_INTR_SHIFT 21

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BAD_STARCH_CFG_INTR [20:20] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BAD_STARCH_CFG_INTR_MASK    0x00100000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BAD_STARCH_CFG_INTR_SHIFT   20

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SCRM_KEY_DONE_INTR [19:19] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SCRM_KEY_DONE_INTR_MASK     0x00080000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SCRM_KEY_DONE_INTR_SHIFT    19

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: BORCH_ERROR_INTR [18:18] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BORCH_ERROR_INTR_MASK       0x00040000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BORCH_ERROR_INTR_SHIFT      18

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: GR_BRIDGE_ERROR_INTR [17:17] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_GR_BRIDGE_ERROR_INTR_MASK   0x00020000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_GR_BRIDGE_ERROR_INTR_SHIFT  17

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: MEM_DMA_INTR [16:16] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_MEM_DMA_INTR_MASK           0x00010000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_MEM_DMA_INTR_SHIFT          16

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX4_INTR [15:15] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX4_INTR_MASK         0x00008000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX4_INTR_SHIFT        15

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX3_INTR [14:14] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX3_INTR_MASK         0x00004000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX3_INTR_SHIFT        14

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX2_INTR [13:13] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX2_INTR_MASK         0x00002000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX2_INTR_SHIFT        13

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX1_INTR [12:12] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX1_INTR_MASK         0x00001000
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX1_INTR_SHIFT        12

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX4_INTR [11:11] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX4_INTR_MASK         0x00000800
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX4_INTR_SHIFT        11

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX3_INTR [10:10] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX3_INTR_MASK         0x00000400
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX3_INTR_SHIFT        10

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX2_INTR [09:09] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX2_INTR_MASK         0x00000200
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX2_INTR_SHIFT        9

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX1_INTR [08:08] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX1_INTR_MASK         0x00000100
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX1_INTR_SHIFT        8

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL2_INTR [07:07] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL2_INTR_MASK       0x00000080
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL2_INTR_SHIFT      7

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL1_INTR [06:06] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL1_INTR_MASK       0x00000040
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL1_INTR_SHIFT      6

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL0_INTR [05:05] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL0_INTR_MASK       0x00000020
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL0_INTR_SHIFT      5

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_ERR_INTR [04:04] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_ERR_INTR_MASK         0x00000010
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_ERR_INTR_SHIFT        4

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_MEM_DMA0_DONE [03:03] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_MEM_DMA0_DONE_MASK    0x00000008
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_MEM_DMA0_DONE_SHIFT   3

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_INTR [02:02] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_INTR_MASK          0x00000004
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_INTR_SHIFT         2

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_RCV_INTR [01:01] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_RCV_INTR_MASK      0x00000002
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_RCV_INTR_SHIFT     1

/* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_XMIT_INTR [00:00] */
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_XMIT_INTR_MASK     0x00000001
#define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_XMIT_INTR_SHIFT    0

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_reserved0_MASK        0xff000000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_reserved0_SHIFT       24

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BOOT_VER_FAIL_MASK [23:23] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_FAIL_MASK_MASK 0x00800000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_FAIL_MASK_SHIFT 23

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BOOT_VER_DONE_MASK [22:22] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_DONE_MASK_MASK 0x00400000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_DONE_MASK_SHIFT 22

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PREMATURE_ARM_REQ_MASK [21:21] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PREMATURE_ARM_REQ_MASK_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PREMATURE_ARM_REQ_MASK_SHIFT 21

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BAD_STARCH_CFG_MASK [20:20] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BAD_STARCH_CFG_MASK_MASK 0x00100000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BAD_STARCH_CFG_MASK_SHIFT 20

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SCRM_KEY_DONE_MASK [19:19] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SCRM_KEY_DONE_MASK_MASK 0x00080000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SCRM_KEY_DONE_MASK_SHIFT 19

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BORCH_ERROR_MASK [18:18] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BORCH_ERROR_MASK_MASK 0x00040000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BORCH_ERROR_MASK_SHIFT 18

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: GR_BRIDGE_ERROR_MASK [17:17] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_GR_BRIDGE_ERROR_MASK_MASK 0x00020000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_GR_BRIDGE_ERROR_MASK_SHIFT 17

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: MEM_DMA_MASK [16:16] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_MEM_DMA_MASK_MASK     0x00010000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_MEM_DMA_MASK_SHIFT    16

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX4_MASK [15:15] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX4_MASK_MASK   0x00008000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX4_MASK_SHIFT  15

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX3_MASK [14:14] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX3_MASK_MASK   0x00004000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX3_MASK_SHIFT  14

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX2_MASK [13:13] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX2_MASK_MASK   0x00002000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX2_MASK_SHIFT  13

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX1_MASK [12:12] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX1_MASK_MASK   0x00001000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX1_MASK_SHIFT  12

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX4_MASK [11:11] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX4_MASK_MASK   0x00000800
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX4_MASK_SHIFT  11

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX3_MASK [10:10] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX3_MASK_MASK   0x00000400
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX3_MASK_SHIFT  10

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX2_MASK [09:09] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX2_MASK_MASK   0x00000200
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX2_MASK_SHIFT  9

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX1_MASK [08:08] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX1_MASK_MASK   0x00000100
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX1_MASK_SHIFT  8

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL2_MASK [07:07] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL2_MASK_MASK 0x00000080
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL2_MASK_SHIFT 7

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL1_MASK [06:06] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL1_MASK_MASK 0x00000040
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL1_MASK_SHIFT 6

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL0_MASK [05:05] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL0_MASK_MASK 0x00000020
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL0_MASK_SHIFT 5

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_ERR_MASK [04:04] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_ERR_MASK_MASK   0x00000010
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_ERR_MASK_SHIFT  4

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_MEM_DMA0_DONE_MASK [03:03] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_MASK [02:02] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_MASK_MASK    0x00000004
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_MASK_SHIFT   2

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_RCV_MASK [01:01] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_RCV_MASK_MASK 0x00000002
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_RCV_MASK_SHIFT 1

/* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_XMIT_MASK [00:00] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_XMIT_MASK_MASK 0x00000001
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_XMIT_MASK_SHIFT 0

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_reserved0_MASK           0xff000000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_reserved0_SHIFT          24

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BOOT_VER_FAIL_MASK [23:23] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_FAIL_MASK_MASK  0x00800000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_FAIL_MASK_SHIFT 23

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BOOT_VER_DONE_MASK [22:22] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_DONE_MASK_MASK  0x00400000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_DONE_MASK_SHIFT 22

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PREMATURE_ARM_REQ_MASK [21:21] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PREMATURE_ARM_REQ_MASK_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PREMATURE_ARM_REQ_MASK_SHIFT 21

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BAD_STARCH_CFG_MASK [20:20] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BAD_STARCH_CFG_MASK_MASK 0x00100000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BAD_STARCH_CFG_MASK_SHIFT 20

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SCRM_KEY_DONE_MASK [19:19] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SCRM_KEY_DONE_MASK_MASK  0x00080000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SCRM_KEY_DONE_MASK_SHIFT 19

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BORCH_ERROR_MASK [18:18] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BORCH_ERROR_MASK_MASK    0x00040000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BORCH_ERROR_MASK_SHIFT   18

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: GR_BRIDGE_ERROR_MASK [17:17] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_GR_BRIDGE_ERROR_MASK_MASK 0x00020000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_GR_BRIDGE_ERROR_MASK_SHIFT 17

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: MEM_DMA_MASK [16:16] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_MEM_DMA_MASK_MASK        0x00010000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_MEM_DMA_MASK_SHIFT       16

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX4_MASK [15:15] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX4_MASK_MASK      0x00008000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX4_MASK_SHIFT     15

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX3_MASK [14:14] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX3_MASK_MASK      0x00004000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX3_MASK_SHIFT     14

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX2_MASK [13:13] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX2_MASK_MASK      0x00002000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX2_MASK_SHIFT     13

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX1_MASK [12:12] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX1_MASK_MASK      0x00001000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX1_MASK_SHIFT     12

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX4_MASK [11:11] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX4_MASK_MASK      0x00000800
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX4_MASK_SHIFT     11

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX3_MASK [10:10] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX3_MASK_MASK      0x00000400
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX3_MASK_SHIFT     10

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX2_MASK [09:09] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX2_MASK_MASK      0x00000200
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX2_MASK_SHIFT     9

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX1_MASK [08:08] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX1_MASK_MASK      0x00000100
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX1_MASK_SHIFT     8

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL2_MASK [07:07] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL2_MASK_MASK    0x00000080
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL2_MASK_SHIFT   7

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL1_MASK [06:06] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL1_MASK_MASK    0x00000040
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL1_MASK_SHIFT   6

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL0_MASK [05:05] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL0_MASK_MASK    0x00000020
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL0_MASK_SHIFT   5

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_ERR_MASK [04:04] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_ERR_MASK_MASK      0x00000010
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_ERR_MASK_SHIFT     4

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_MEM_DMA0_DONE_MASK [03:03] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_MASK [02:02] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_MASK_MASK       0x00000004
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_MASK_SHIFT      2

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_RCV_MASK [01:01] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_RCV_MASK_MASK   0x00000002
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_RCV_MASK_SHIFT  1

/* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_XMIT_MASK [00:00] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_XMIT_MASK_MASK  0x00000001
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_XMIT_MASK_SHIFT 0

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_reserved0_MASK         0xff000000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT        24

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BOOT_VER_FAIL_MASK [23:23] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_FAIL_MASK_MASK 0x00800000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_FAIL_MASK_SHIFT 23

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BOOT_VER_DONE_MASK [22:22] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_DONE_MASK_MASK 0x00400000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_DONE_MASK_SHIFT 22

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PREMATURE_ARM_REQ_MASK [21:21] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_SHIFT 21

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BAD_STARCH_CFG_MASK [20:20] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BAD_STARCH_CFG_MASK_MASK 0x00100000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BAD_STARCH_CFG_MASK_SHIFT 20

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SCRM_KEY_DONE_MASK [19:19] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SCRM_KEY_DONE_MASK_MASK 0x00080000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SCRM_KEY_DONE_MASK_SHIFT 19

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BORCH_ERROR_MASK [18:18] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BORCH_ERROR_MASK_MASK  0x00040000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BORCH_ERROR_MASK_SHIFT 18

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: GR_BRIDGE_ERROR_MASK [17:17] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_MASK 0x00020000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_SHIFT 17

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: MEM_DMA_MASK [16:16] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_MEM_DMA_MASK_MASK      0x00010000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_MEM_DMA_MASK_SHIFT     16

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX4_MASK [15:15] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX4_MASK_MASK    0x00008000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX4_MASK_SHIFT   15

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX3_MASK [14:14] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX3_MASK_MASK    0x00004000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX3_MASK_SHIFT   14

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX2_MASK [13:13] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX2_MASK_MASK    0x00002000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX2_MASK_SHIFT   13

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX1_MASK [12:12] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX1_MASK_MASK    0x00001000
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX1_MASK_SHIFT   12

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX4_MASK [11:11] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX4_MASK_MASK    0x00000800
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX4_MASK_SHIFT   11

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX3_MASK [10:10] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX3_MASK_MASK    0x00000400
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX3_MASK_SHIFT   10

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX2_MASK [09:09] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX2_MASK_MASK    0x00000200
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX2_MASK_SHIFT   9

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX1_MASK [08:08] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX1_MASK_MASK    0x00000100
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX1_MASK_SHIFT   8

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL2_MASK [07:07] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL2_MASK_MASK  0x00000080
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL2_MASK_SHIFT 7

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL1_MASK [06:06] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL1_MASK_MASK  0x00000040
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL1_MASK_SHIFT 6

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL0_MASK [05:05] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL0_MASK_MASK  0x00000020
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL0_MASK_SHIFT 5

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_ERR_MASK [04:04] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_ERR_MASK_MASK    0x00000010
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_ERR_MASK_SHIFT   4

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_MEM_DMA0_DONE_MASK [03:03] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_MASK [02:02] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_MASK_MASK     0x00000004
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_MASK_SHIFT    2

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_RCV_MASK [01:01] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_RCV_MASK_MASK 0x00000002
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_RCV_MASK_SHIFT 1

/* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_XMIT_MASK [00:00] */
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_XMIT_MASK_MASK 0x00000001
#define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_XMIT_MASK_SHIFT 0

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: PCI_STATUS :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_reserved0_MASK             0xff000000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_reserved0_SHIFT            24

/* WRAP_MISC_INTR2 :: PCI_STATUS :: BOOT_VER_FAIL_INTR [23:23] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_FAIL_INTR_MASK    0x00800000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_FAIL_INTR_SHIFT   23

/* WRAP_MISC_INTR2 :: PCI_STATUS :: BOOT_VER_DONE_INTR [22:22] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_DONE_INTR_MASK    0x00400000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_DONE_INTR_SHIFT   22

/* WRAP_MISC_INTR2 :: PCI_STATUS :: PREMATURE_ARM_REQ_INTR [21:21] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PREMATURE_ARM_REQ_INTR_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PREMATURE_ARM_REQ_INTR_SHIFT 21

/* WRAP_MISC_INTR2 :: PCI_STATUS :: BAD_STARCH_CFG_INTR [20:20] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BAD_STARCH_CFG_INTR_MASK   0x00100000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BAD_STARCH_CFG_INTR_SHIFT  20

/* WRAP_MISC_INTR2 :: PCI_STATUS :: SCRM_KEY_DONE_INTR [19:19] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SCRM_KEY_DONE_INTR_MASK    0x00080000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SCRM_KEY_DONE_INTR_SHIFT   19

/* WRAP_MISC_INTR2 :: PCI_STATUS :: BORCH_ERROR_INTR [18:18] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BORCH_ERROR_INTR_MASK      0x00040000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BORCH_ERROR_INTR_SHIFT     18

/* WRAP_MISC_INTR2 :: PCI_STATUS :: GR_BRIDGE_ERROR_INTR [17:17] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_GR_BRIDGE_ERROR_INTR_MASK  0x00020000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_GR_BRIDGE_ERROR_INTR_SHIFT 17

/* WRAP_MISC_INTR2 :: PCI_STATUS :: MEM_DMA_INTR [16:16] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_MEM_DMA_INTR_MASK          0x00010000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_MEM_DMA_INTR_SHIFT         16

/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX4_INTR [15:15] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX4_INTR_MASK        0x00008000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX4_INTR_SHIFT       15

/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX3_INTR [14:14] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX3_INTR_MASK        0x00004000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX3_INTR_SHIFT       14

/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX2_INTR [13:13] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX2_INTR_MASK        0x00002000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX2_INTR_SHIFT       13

/* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX1_INTR [12:12] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX1_INTR_MASK        0x00001000
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX1_INTR_SHIFT       12

/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX4_INTR [11:11] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX4_INTR_MASK        0x00000800
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX4_INTR_SHIFT       11

/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX3_INTR [10:10] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX3_INTR_MASK        0x00000400
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX3_INTR_SHIFT       10

/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX2_INTR [09:09] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX2_INTR_MASK        0x00000200
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX2_INTR_SHIFT       9

/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX1_INTR [08:08] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX1_INTR_MASK        0x00000100
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX1_INTR_SHIFT       8

/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL2_INTR [07:07] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL2_INTR_MASK      0x00000080
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL2_INTR_SHIFT     7

/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL1_INTR [06:06] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL1_INTR_MASK      0x00000040
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL1_INTR_SHIFT     6

/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL0_INTR [05:05] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL0_INTR_MASK      0x00000020
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL0_INTR_SHIFT     5

/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_ERR_INTR [04:04] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_ERR_INTR_MASK        0x00000010
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_ERR_INTR_SHIFT       4

/* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_MEM_DMA0_DONE [03:03] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_MEM_DMA0_DONE_MASK   0x00000008
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_MEM_DMA0_DONE_SHIFT  3

/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_INTR [02:02] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_INTR_MASK         0x00000004
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_INTR_SHIFT        2

/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_RCV_INTR [01:01] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_RCV_INTR_MASK     0x00000002
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_RCV_INTR_SHIFT    1

/* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_XMIT_INTR [00:00] */
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_XMIT_INTR_MASK    0x00000001
#define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_XMIT_INTR_SHIFT   0

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: PCI_SET :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_reserved0_MASK                0xff000000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_reserved0_SHIFT               24

/* WRAP_MISC_INTR2 :: PCI_SET :: BOOT_VER_FAIL_INTR [23:23] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_FAIL_INTR_MASK       0x00800000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_FAIL_INTR_SHIFT      23

/* WRAP_MISC_INTR2 :: PCI_SET :: BOOT_VER_DONE_INTR [22:22] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_DONE_INTR_MASK       0x00400000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_DONE_INTR_SHIFT      22

/* WRAP_MISC_INTR2 :: PCI_SET :: PREMATURE_ARM_REQ_INTR [21:21] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PREMATURE_ARM_REQ_INTR_MASK   0x00200000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PREMATURE_ARM_REQ_INTR_SHIFT  21

/* WRAP_MISC_INTR2 :: PCI_SET :: BAD_STARCH_CFG_INTR [20:20] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BAD_STARCH_CFG_INTR_MASK      0x00100000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BAD_STARCH_CFG_INTR_SHIFT     20

/* WRAP_MISC_INTR2 :: PCI_SET :: SCRM_KEY_DONE_INTR [19:19] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SCRM_KEY_DONE_INTR_MASK       0x00080000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SCRM_KEY_DONE_INTR_SHIFT      19

/* WRAP_MISC_INTR2 :: PCI_SET :: BORCH_ERROR_INTR [18:18] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BORCH_ERROR_INTR_MASK         0x00040000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_BORCH_ERROR_INTR_SHIFT        18

/* WRAP_MISC_INTR2 :: PCI_SET :: GR_BRIDGE_ERROR_INTR [17:17] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_GR_BRIDGE_ERROR_INTR_MASK     0x00020000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_GR_BRIDGE_ERROR_INTR_SHIFT    17

/* WRAP_MISC_INTR2 :: PCI_SET :: MEM_DMA_INTR [16:16] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_MEM_DMA_INTR_MASK             0x00010000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_MEM_DMA_INTR_SHIFT            16

/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX4_INTR [15:15] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX4_INTR_MASK           0x00008000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX4_INTR_SHIFT          15

/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX3_INTR [14:14] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX3_INTR_MASK           0x00004000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX3_INTR_SHIFT          14

/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX2_INTR [13:13] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX2_INTR_MASK           0x00002000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX2_INTR_SHIFT          13

/* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX1_INTR [12:12] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX1_INTR_MASK           0x00001000
#define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX1_INTR_SHIFT          12

/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX4_INTR [11:11] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX4_INTR_MASK           0x00000800
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX4_INTR_SHIFT          11

/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX3_INTR [10:10] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX3_INTR_MASK           0x00000400
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX3_INTR_SHIFT          10

/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX2_INTR [09:09] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX2_INTR_MASK           0x00000200
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX2_INTR_SHIFT          9

/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX1_INTR [08:08] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX1_INTR_MASK           0x00000100
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX1_INTR_SHIFT          8

/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL2_INTR [07:07] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL2_INTR_MASK         0x00000080
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL2_INTR_SHIFT        7

/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL1_INTR [06:06] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL1_INTR_MASK         0x00000040
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL1_INTR_SHIFT        6

/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL0_INTR [05:05] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL0_INTR_MASK         0x00000020
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL0_INTR_SHIFT        5

/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_ERR_INTR [04:04] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_ERR_INTR_MASK           0x00000010
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_ERR_INTR_SHIFT          4

/* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_MEM_DMA0_DONE [03:03] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_MEM_DMA0_DONE_MASK      0x00000008
#define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_MEM_DMA0_DONE_SHIFT     3

/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_INTR [02:02] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_INTR_MASK            0x00000004
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_INTR_SHIFT           2

/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_RCV_INTR [01:01] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_RCV_INTR_MASK        0x00000002
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_RCV_INTR_SHIFT       1

/* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_XMIT_INTR [00:00] */
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_XMIT_INTR_MASK       0x00000001
#define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_XMIT_INTR_SHIFT      0

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: PCI_CLEAR :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_reserved0_MASK              0xff000000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_reserved0_SHIFT             24

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BOOT_VER_FAIL_INTR [23:23] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_FAIL_INTR_MASK     0x00800000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_FAIL_INTR_SHIFT    23

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BOOT_VER_DONE_INTR [22:22] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_DONE_INTR_MASK     0x00400000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_DONE_INTR_SHIFT    22

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PREMATURE_ARM_REQ_INTR [21:21] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PREMATURE_ARM_REQ_INTR_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PREMATURE_ARM_REQ_INTR_SHIFT 21

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BAD_STARCH_CFG_INTR [20:20] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BAD_STARCH_CFG_INTR_MASK    0x00100000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BAD_STARCH_CFG_INTR_SHIFT   20

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SCRM_KEY_DONE_INTR [19:19] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SCRM_KEY_DONE_INTR_MASK     0x00080000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SCRM_KEY_DONE_INTR_SHIFT    19

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: BORCH_ERROR_INTR [18:18] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BORCH_ERROR_INTR_MASK       0x00040000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BORCH_ERROR_INTR_SHIFT      18

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: GR_BRIDGE_ERROR_INTR [17:17] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_GR_BRIDGE_ERROR_INTR_MASK   0x00020000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_GR_BRIDGE_ERROR_INTR_SHIFT  17

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: MEM_DMA_INTR [16:16] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_MEM_DMA_INTR_MASK           0x00010000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_MEM_DMA_INTR_SHIFT          16

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX4_INTR [15:15] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX4_INTR_MASK         0x00008000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX4_INTR_SHIFT        15

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX3_INTR [14:14] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX3_INTR_MASK         0x00004000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX3_INTR_SHIFT        14

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX2_INTR [13:13] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX2_INTR_MASK         0x00002000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX2_INTR_SHIFT        13

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX1_INTR [12:12] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX1_INTR_MASK         0x00001000
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX1_INTR_SHIFT        12

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX4_INTR [11:11] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX4_INTR_MASK         0x00000800
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX4_INTR_SHIFT        11

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX3_INTR [10:10] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX3_INTR_MASK         0x00000400
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX3_INTR_SHIFT        10

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX2_INTR [09:09] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX2_INTR_MASK         0x00000200
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX2_INTR_SHIFT        9

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX1_INTR [08:08] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX1_INTR_MASK         0x00000100
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX1_INTR_SHIFT        8

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL2_INTR [07:07] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL2_INTR_MASK       0x00000080
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL2_INTR_SHIFT      7

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL1_INTR [06:06] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL1_INTR_MASK       0x00000040
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL1_INTR_SHIFT      6

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL0_INTR [05:05] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL0_INTR_MASK       0x00000020
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL0_INTR_SHIFT      5

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_ERR_INTR [04:04] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_ERR_INTR_MASK         0x00000010
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_ERR_INTR_SHIFT        4

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_MEM_DMA0_DONE [03:03] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_MEM_DMA0_DONE_MASK    0x00000008
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_MEM_DMA0_DONE_SHIFT   3

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_INTR [02:02] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_INTR_MASK          0x00000004
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_INTR_SHIFT         2

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_RCV_INTR [01:01] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_RCV_INTR_MASK      0x00000002
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_RCV_INTR_SHIFT     1

/* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_XMIT_INTR [00:00] */
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_XMIT_INTR_MASK     0x00000001
#define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_XMIT_INTR_SHIFT    0

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_reserved0_MASK        0xff000000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_reserved0_SHIFT       24

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BOOT_VER_FAIL_MASK [23:23] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_FAIL_MASK_MASK 0x00800000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_FAIL_MASK_SHIFT 23

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BOOT_VER_DONE_MASK [22:22] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_DONE_MASK_MASK 0x00400000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_DONE_MASK_SHIFT 22

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PREMATURE_ARM_REQ_MASK [21:21] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PREMATURE_ARM_REQ_MASK_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PREMATURE_ARM_REQ_MASK_SHIFT 21

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BAD_STARCH_CFG_MASK [20:20] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BAD_STARCH_CFG_MASK_MASK 0x00100000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BAD_STARCH_CFG_MASK_SHIFT 20

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SCRM_KEY_DONE_MASK [19:19] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SCRM_KEY_DONE_MASK_MASK 0x00080000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SCRM_KEY_DONE_MASK_SHIFT 19

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BORCH_ERROR_MASK [18:18] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BORCH_ERROR_MASK_MASK 0x00040000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BORCH_ERROR_MASK_SHIFT 18

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: GR_BRIDGE_ERROR_MASK [17:17] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_GR_BRIDGE_ERROR_MASK_MASK 0x00020000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_GR_BRIDGE_ERROR_MASK_SHIFT 17

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: MEM_DMA_MASK [16:16] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_MEM_DMA_MASK_MASK     0x00010000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_MEM_DMA_MASK_SHIFT    16

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX4_MASK [15:15] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX4_MASK_MASK   0x00008000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX4_MASK_SHIFT  15

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX3_MASK [14:14] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX3_MASK_MASK   0x00004000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX3_MASK_SHIFT  14

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX2_MASK [13:13] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX2_MASK_MASK   0x00002000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX2_MASK_SHIFT  13

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX1_MASK [12:12] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX1_MASK_MASK   0x00001000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX1_MASK_SHIFT  12

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX4_MASK [11:11] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX4_MASK_MASK   0x00000800
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX4_MASK_SHIFT  11

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX3_MASK [10:10] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX3_MASK_MASK   0x00000400
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX3_MASK_SHIFT  10

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX2_MASK [09:09] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX2_MASK_MASK   0x00000200
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX2_MASK_SHIFT  9

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX1_MASK [08:08] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX1_MASK_MASK   0x00000100
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX1_MASK_SHIFT  8

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL2_MASK [07:07] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL2_MASK_MASK 0x00000080
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL2_MASK_SHIFT 7

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL1_MASK [06:06] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL1_MASK_MASK 0x00000040
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL1_MASK_SHIFT 6

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL0_MASK [05:05] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL0_MASK_MASK 0x00000020
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL0_MASK_SHIFT 5

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_ERR_MASK [04:04] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_ERR_MASK_MASK   0x00000010
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_ERR_MASK_SHIFT  4

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_MEM_DMA0_DONE_MASK [03:03] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_MASK [02:02] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_MASK_MASK    0x00000004
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_MASK_SHIFT   2

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_RCV_MASK [01:01] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_RCV_MASK_MASK 0x00000002
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_RCV_MASK_SHIFT 1

/* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_XMIT_MASK [00:00] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_XMIT_MASK_MASK 0x00000001
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_XMIT_MASK_SHIFT 0

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_reserved0_MASK           0xff000000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_reserved0_SHIFT          24

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BOOT_VER_FAIL_MASK [23:23] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_FAIL_MASK_MASK  0x00800000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_FAIL_MASK_SHIFT 23

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BOOT_VER_DONE_MASK [22:22] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_DONE_MASK_MASK  0x00400000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_DONE_MASK_SHIFT 22

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PREMATURE_ARM_REQ_MASK [21:21] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PREMATURE_ARM_REQ_MASK_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PREMATURE_ARM_REQ_MASK_SHIFT 21

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BAD_STARCH_CFG_MASK [20:20] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BAD_STARCH_CFG_MASK_MASK 0x00100000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BAD_STARCH_CFG_MASK_SHIFT 20

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SCRM_KEY_DONE_MASK [19:19] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SCRM_KEY_DONE_MASK_MASK  0x00080000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SCRM_KEY_DONE_MASK_SHIFT 19

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BORCH_ERROR_MASK [18:18] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BORCH_ERROR_MASK_MASK    0x00040000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BORCH_ERROR_MASK_SHIFT   18

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: GR_BRIDGE_ERROR_MASK [17:17] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_GR_BRIDGE_ERROR_MASK_MASK 0x00020000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_GR_BRIDGE_ERROR_MASK_SHIFT 17

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: MEM_DMA_MASK [16:16] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_MEM_DMA_MASK_MASK        0x00010000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_MEM_DMA_MASK_SHIFT       16

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX4_MASK [15:15] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX4_MASK_MASK      0x00008000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX4_MASK_SHIFT     15

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX3_MASK [14:14] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX3_MASK_MASK      0x00004000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX3_MASK_SHIFT     14

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX2_MASK [13:13] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX2_MASK_MASK      0x00002000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX2_MASK_SHIFT     13

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX1_MASK [12:12] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX1_MASK_MASK      0x00001000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX1_MASK_SHIFT     12

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX4_MASK [11:11] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX4_MASK_MASK      0x00000800
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX4_MASK_SHIFT     11

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX3_MASK [10:10] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX3_MASK_MASK      0x00000400
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX3_MASK_SHIFT     10

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX2_MASK [09:09] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX2_MASK_MASK      0x00000200
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX2_MASK_SHIFT     9

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX1_MASK [08:08] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX1_MASK_MASK      0x00000100
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX1_MASK_SHIFT     8

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL2_MASK [07:07] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL2_MASK_MASK    0x00000080
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL2_MASK_SHIFT   7

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL1_MASK [06:06] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL1_MASK_MASK    0x00000040
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL1_MASK_SHIFT   6

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL0_MASK [05:05] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL0_MASK_MASK    0x00000020
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL0_MASK_SHIFT   5

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_ERR_MASK [04:04] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_ERR_MASK_MASK      0x00000010
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_ERR_MASK_SHIFT     4

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_MEM_DMA0_DONE_MASK [03:03] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_MASK [02:02] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_MASK_MASK       0x00000004
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_MASK_SHIFT      2

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_RCV_MASK [01:01] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_RCV_MASK_MASK   0x00000002
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_RCV_MASK_SHIFT  1

/* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_XMIT_MASK [00:00] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_XMIT_MASK_MASK  0x00000001
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_XMIT_MASK_SHIFT 0

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:24] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_reserved0_MASK         0xff000000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT        24

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BOOT_VER_FAIL_MASK [23:23] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_FAIL_MASK_MASK 0x00800000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_FAIL_MASK_SHIFT 23

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BOOT_VER_DONE_MASK [22:22] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_DONE_MASK_MASK 0x00400000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_DONE_MASK_SHIFT 22

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PREMATURE_ARM_REQ_MASK [21:21] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_MASK 0x00200000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_SHIFT 21

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BAD_STARCH_CFG_MASK [20:20] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BAD_STARCH_CFG_MASK_MASK 0x00100000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BAD_STARCH_CFG_MASK_SHIFT 20

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SCRM_KEY_DONE_MASK [19:19] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SCRM_KEY_DONE_MASK_MASK 0x00080000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SCRM_KEY_DONE_MASK_SHIFT 19

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BORCH_ERROR_MASK [18:18] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BORCH_ERROR_MASK_MASK  0x00040000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BORCH_ERROR_MASK_SHIFT 18

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: GR_BRIDGE_ERROR_MASK [17:17] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_MASK 0x00020000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_SHIFT 17

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: MEM_DMA_MASK [16:16] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_MEM_DMA_MASK_MASK      0x00010000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_MEM_DMA_MASK_SHIFT     16

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX4_MASK [15:15] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX4_MASK_MASK    0x00008000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX4_MASK_SHIFT   15

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX3_MASK [14:14] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX3_MASK_MASK    0x00004000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX3_MASK_SHIFT   14

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX2_MASK [13:13] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX2_MASK_MASK    0x00002000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX2_MASK_SHIFT   13

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX1_MASK [12:12] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX1_MASK_MASK    0x00001000
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX1_MASK_SHIFT   12

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX4_MASK [11:11] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX4_MASK_MASK    0x00000800
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX4_MASK_SHIFT   11

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX3_MASK [10:10] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX3_MASK_MASK    0x00000400
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX3_MASK_SHIFT   10

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX2_MASK [09:09] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX2_MASK_MASK    0x00000200
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX2_MASK_SHIFT   9

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX1_MASK [08:08] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX1_MASK_MASK    0x00000100
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX1_MASK_SHIFT   8

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL2_MASK [07:07] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL2_MASK_MASK  0x00000080
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL2_MASK_SHIFT 7

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL1_MASK [06:06] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL1_MASK_MASK  0x00000040
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL1_MASK_SHIFT 6

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL0_MASK [05:05] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL0_MASK_MASK  0x00000020
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL0_MASK_SHIFT 5

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_ERR_MASK [04:04] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_ERR_MASK_MASK    0x00000010
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_ERR_MASK_SHIFT   4

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_MEM_DMA0_DONE_MASK [03:03] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_MASK [02:02] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_MASK_MASK     0x00000004
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_MASK_SHIFT    2

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_RCV_MASK [01:01] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_RCV_MASK_MASK 0x00000002
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_RCV_MASK_SHIFT 1

/* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_XMIT_MASK [00:00] */
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_XMIT_MASK_MASK 0x00000001
#define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_XMIT_MASK_SHIFT 0

#endif /* #ifndef BCHP_WRAP_MISC_INTR2_H__ */

/* End of File */
