/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_pri_arb_mips_l2_regs.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:14p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:43:15 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:14p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_PRI_ARB_MIPS_L2_REGS_H__
#define BCHP_PRI_ARB_MIPS_L2_REGS_H__

/***************************************************************************
 *PRI_ARB_MIPS_L2_REGS - PRIMARY_ARB L2 (MIPS) Interrupt Registers
 ***************************************************************************/
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS     0x0040ce00 /* CPU interrupt Status Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET        0x0040ce04 /* CPU interrupt Set Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR      0x0040ce08 /* CPU interrupt Clear Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS 0x0040ce0c /* CPU interrupt Mask Status Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET   0x0040ce10 /* CPU interrupt Mask Set Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR 0x0040ce14 /* CPU interrupt Mask Clear Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS     0x0040ce18 /* PCI interrupt Status Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET        0x0040ce1c /* PCI interrupt Set Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR      0x0040ce20 /* PCI interrupt Clear Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS 0x0040ce24 /* PCI interrupt Mask Status Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET   0x0040ce28 /* PCI interrupt Mask Set Register */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR 0x0040ce2c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_reserved0_MASK        0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_reserved0_SHIFT       9

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ALIAS_INTR [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ALIAS_INTR_MASK       0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ALIAS_INTR_SHIFT      8

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: WR_TIMEOUT_1_INTR [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_1_INTR_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_1_INTR_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: WR_TIMEOUT_0_INTR [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_0_INTR_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_0_INTR_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: TRACE_DONE_INTR [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_DONE_INTR_MASK  0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_DONE_INTR_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: TRACE_TRIG_INTR [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_TRIG_INTR_MASK  0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_TRIG_INTR_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH3_INTR [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH3_INTR_MASK       0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH3_INTR_SHIFT      3

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH2_INTR [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH2_INTR_MASK       0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH2_INTR_SHIFT      2

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH1_INTR [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH1_INTR_MASK       0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH1_INTR_SHIFT      1

/* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH0_INTR [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH0_INTR_MASK       0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH0_INTR_SHIFT      0

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_reserved0_MASK           0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_reserved0_SHIFT          9

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ALIAS_INTR [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ALIAS_INTR_MASK          0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ALIAS_INTR_SHIFT         8

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: WR_TIMEOUT_1_INTR [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_1_INTR_MASK   0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_1_INTR_SHIFT  7

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: WR_TIMEOUT_0_INTR [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_0_INTR_MASK   0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_0_INTR_SHIFT  6

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: TRACE_DONE_INTR [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_DONE_INTR_MASK     0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_DONE_INTR_SHIFT    5

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: TRACE_TRIG_INTR [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_TRIG_INTR_MASK     0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_TRIG_INTR_SHIFT    4

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH3_INTR [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH3_INTR_MASK          0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH3_INTR_SHIFT         3

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH2_INTR [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH2_INTR_MASK          0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH2_INTR_SHIFT         2

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH1_INTR [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH1_INTR_MASK          0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH1_INTR_SHIFT         1

/* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH0_INTR [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH0_INTR_MASK          0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH0_INTR_SHIFT         0

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_reserved0_MASK         0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_reserved0_SHIFT        9

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ALIAS_INTR [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ALIAS_INTR_MASK        0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ALIAS_INTR_SHIFT       8

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: WR_TIMEOUT_1_INTR [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_1_INTR_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_1_INTR_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: WR_TIMEOUT_0_INTR [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_0_INTR_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_0_INTR_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: TRACE_DONE_INTR [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_DONE_INTR_MASK   0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_DONE_INTR_SHIFT  5

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: TRACE_TRIG_INTR [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_TRIG_INTR_MASK   0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_TRIG_INTR_SHIFT  4

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH3_INTR [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH3_INTR_MASK        0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH3_INTR_SHIFT       3

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH2_INTR [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH2_INTR_MASK        0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH2_INTR_SHIFT       2

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH1_INTR [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH1_INTR_MASK        0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH1_INTR_SHIFT       1

/* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH0_INTR [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH0_INTR_MASK        0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH0_INTR_SHIFT       0

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_reserved0_MASK   0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_reserved0_SHIFT  9

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ALIAS_MASK [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ALIAS_MASK_MASK  0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ALIAS_MASK_SHIFT 8

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: WR_TIMEOUT_1_MASK [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_1_MASK_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_1_MASK_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: WR_TIMEOUT_0_MASK [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_0_MASK_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_0_MASK_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: TRACE_DONE_MASK [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_DONE_MASK_MASK 0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_DONE_MASK_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: TRACE_TRIG_MASK [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_TRIG_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_TRIG_MASK_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH3_MASK_MASK  0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH3_MASK_SHIFT 3

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH2_MASK_MASK  0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH2_MASK_SHIFT 2

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH1_MASK_MASK  0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH1_MASK_SHIFT 1

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH0_MASK_MASK  0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH0_MASK_SHIFT 0

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_reserved0_MASK      0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_reserved0_SHIFT     9

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ALIAS_MASK [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ALIAS_MASK_MASK     0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ALIAS_MASK_SHIFT    8

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: WR_TIMEOUT_1_MASK [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_1_MASK_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_1_MASK_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: WR_TIMEOUT_0_MASK [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_0_MASK_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_0_MASK_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: TRACE_DONE_MASK [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_DONE_MASK_MASK 0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_DONE_MASK_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: TRACE_TRIG_MASK [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_TRIG_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_TRIG_MASK_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH3_MASK_MASK     0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH3_MASK_SHIFT    3

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH2_MASK_MASK     0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH2_MASK_SHIFT    2

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH1_MASK_MASK     0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH1_MASK_SHIFT    1

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH0_MASK_MASK     0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH0_MASK_SHIFT    0

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_reserved0_MASK    0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_reserved0_SHIFT   9

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ALIAS_MASK [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ALIAS_MASK_MASK   0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ALIAS_MASK_SHIFT  8

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: WR_TIMEOUT_1_MASK [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_1_MASK_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_1_MASK_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: WR_TIMEOUT_0_MASK [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_0_MASK_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_0_MASK_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: TRACE_DONE_MASK [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_DONE_MASK_MASK 0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_DONE_MASK_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: TRACE_TRIG_MASK [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_TRIG_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_TRIG_MASK_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH3_MASK_MASK   0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH3_MASK_SHIFT  3

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH2_MASK_MASK   0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH2_MASK_SHIFT  2

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH1_MASK_MASK   0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH1_MASK_SHIFT  1

/* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH0_MASK_MASK   0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH0_MASK_SHIFT  0

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_reserved0_MASK        0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_reserved0_SHIFT       9

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ALIAS_INTR [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ALIAS_INTR_MASK       0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ALIAS_INTR_SHIFT      8

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: WR_TIMEOUT_1_INTR [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_1_INTR_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_1_INTR_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: WR_TIMEOUT_0_INTR [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_0_INTR_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_0_INTR_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: TRACE_DONE_INTR [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_DONE_INTR_MASK  0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_DONE_INTR_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: TRACE_TRIG_INTR [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_TRIG_INTR_MASK  0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_TRIG_INTR_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH3_INTR [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH3_INTR_MASK       0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH3_INTR_SHIFT      3

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH2_INTR [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH2_INTR_MASK       0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH2_INTR_SHIFT      2

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH1_INTR [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH1_INTR_MASK       0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH1_INTR_SHIFT      1

/* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH0_INTR [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH0_INTR_MASK       0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH0_INTR_SHIFT      0

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_reserved0_MASK           0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_reserved0_SHIFT          9

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ALIAS_INTR [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ALIAS_INTR_MASK          0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ALIAS_INTR_SHIFT         8

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: WR_TIMEOUT_1_INTR [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_1_INTR_MASK   0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_1_INTR_SHIFT  7

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: WR_TIMEOUT_0_INTR [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_0_INTR_MASK   0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_0_INTR_SHIFT  6

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: TRACE_DONE_INTR [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_DONE_INTR_MASK     0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_DONE_INTR_SHIFT    5

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: TRACE_TRIG_INTR [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_TRIG_INTR_MASK     0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_TRIG_INTR_SHIFT    4

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH3_INTR [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH3_INTR_MASK          0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH3_INTR_SHIFT         3

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH2_INTR [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH2_INTR_MASK          0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH2_INTR_SHIFT         2

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH1_INTR [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH1_INTR_MASK          0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH1_INTR_SHIFT         1

/* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH0_INTR [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH0_INTR_MASK          0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH0_INTR_SHIFT         0

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_reserved0_MASK         0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_reserved0_SHIFT        9

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ALIAS_INTR [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ALIAS_INTR_MASK        0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ALIAS_INTR_SHIFT       8

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: WR_TIMEOUT_1_INTR [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_1_INTR_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_1_INTR_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: WR_TIMEOUT_0_INTR [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_0_INTR_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_0_INTR_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: TRACE_DONE_INTR [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_DONE_INTR_MASK   0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_DONE_INTR_SHIFT  5

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: TRACE_TRIG_INTR [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_TRIG_INTR_MASK   0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_TRIG_INTR_SHIFT  4

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH3_INTR [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH3_INTR_MASK        0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH3_INTR_SHIFT       3

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH2_INTR [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH2_INTR_MASK        0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH2_INTR_SHIFT       2

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH1_INTR [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH1_INTR_MASK        0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH1_INTR_SHIFT       1

/* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH0_INTR [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH0_INTR_MASK        0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH0_INTR_SHIFT       0

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_reserved0_MASK   0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_reserved0_SHIFT  9

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ALIAS_MASK [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ALIAS_MASK_MASK  0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ALIAS_MASK_SHIFT 8

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: WR_TIMEOUT_1_MASK [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_1_MASK_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_1_MASK_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: WR_TIMEOUT_0_MASK [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_0_MASK_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_0_MASK_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: TRACE_DONE_MASK [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_DONE_MASK_MASK 0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_DONE_MASK_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: TRACE_TRIG_MASK [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_TRIG_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_TRIG_MASK_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH3_MASK_MASK  0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH3_MASK_SHIFT 3

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH2_MASK_MASK  0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH2_MASK_SHIFT 2

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH1_MASK_MASK  0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH1_MASK_SHIFT 1

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH0_MASK_MASK  0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH0_MASK_SHIFT 0

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_reserved0_MASK      0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_reserved0_SHIFT     9

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ALIAS_MASK [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ALIAS_MASK_MASK     0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ALIAS_MASK_SHIFT    8

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: WR_TIMEOUT_1_MASK [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_1_MASK_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_1_MASK_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: WR_TIMEOUT_0_MASK [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_0_MASK_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_0_MASK_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: TRACE_DONE_MASK [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_DONE_MASK_MASK 0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_DONE_MASK_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: TRACE_TRIG_MASK [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_TRIG_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_TRIG_MASK_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH3_MASK_MASK     0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH3_MASK_SHIFT    3

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH2_MASK_MASK     0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH2_MASK_SHIFT    2

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH1_MASK_MASK     0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH1_MASK_SHIFT    1

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH0_MASK_MASK     0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH0_MASK_SHIFT    0

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: reserved0 [31:09] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_reserved0_MASK    0xfffffe00
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_reserved0_SHIFT   9

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ALIAS_MASK [08:08] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ALIAS_MASK_MASK   0x00000100
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ALIAS_MASK_SHIFT  8

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: WR_TIMEOUT_1_MASK [07:07] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_1_MASK_MASK 0x00000080
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_1_MASK_SHIFT 7

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: WR_TIMEOUT_0_MASK [06:06] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_0_MASK_MASK 0x00000040
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_0_MASK_SHIFT 6

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: TRACE_DONE_MASK [05:05] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_DONE_MASK_MASK 0x00000020
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_DONE_MASK_SHIFT 5

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: TRACE_TRIG_MASK [04:04] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_TRIG_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_TRIG_MASK_SHIFT 4

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH3_MASK_MASK   0x00000008
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH3_MASK_SHIFT  3

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH2_MASK_MASK   0x00000004
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH2_MASK_SHIFT  2

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH1_MASK_MASK   0x00000002
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH1_MASK_SHIFT  1

/* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH0_MASK_MASK   0x00000001
#define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH0_MASK_SHIFT  0

#endif /* #ifndef BCHP_PRI_ARB_MIPS_L2_REGS_H__ */

/* End of File */
