/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_avd_intr2_0.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 7:57p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:50 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 7:57p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_AVD_INTR2_0_H__
#define BCHP_AVD_INTR2_0_H__

/***************************************************************************
 *AVD_INTR2_0
 ***************************************************************************/
#define BCHP_AVD_INTR2_0_CPU_STATUS              0x00900000 /* CPU interrupt Status Register */
#define BCHP_AVD_INTR2_0_CPU_SET                 0x00900004 /* CPU interrupt Set Register */
#define BCHP_AVD_INTR2_0_CPU_CLEAR               0x00900008 /* CPU interrupt Clear Register */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS         0x0090000c /* CPU interrupt Mask Status Register */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET            0x00900010 /* CPU interrupt Mask Set Register */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR          0x00900014 /* CPU interrupt Mask Clear Register */
#define BCHP_AVD_INTR2_0_PCI_STATUS              0x00900018 /* PCI interrupt Status Register */
#define BCHP_AVD_INTR2_0_PCI_SET                 0x0090001c /* PCI interrupt Set Register */
#define BCHP_AVD_INTR2_0_PCI_CLEAR               0x00900020 /* PCI interrupt Clear Register */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS         0x00900024 /* PCI interrupt Mask Status Register */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET            0x00900028 /* PCI interrupt Mask Set Register */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR          0x0090002c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR15_MASK             0x80000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR15_SHIFT            31

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR14_MASK             0x40000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR14_SHIFT            30

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR13_MASK             0x20000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR13_SHIFT            29

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR12_MASK             0x10000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR12_SHIFT            28

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR11_MASK             0x08000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR11_SHIFT            27

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR10_MASK             0x04000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR10_SHIFT            26

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR9_MASK              0x02000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR9_SHIFT             25

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR8_MASK              0x01000000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR8_SHIFT             24

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR7_MASK              0x00800000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR7_SHIFT             23

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR6_MASK              0x00400000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR6_SHIFT             22

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR5_MASK              0x00200000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR5_SHIFT             21

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR4_MASK              0x00100000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR4_SHIFT             20

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR3_MASK              0x00080000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR3_SHIFT             19

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR2_MASK              0x00040000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR2_SHIFT             18

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR1_MASK              0x00020000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR1_SHIFT             17

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR0_MASK              0x00010000
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR0_SHIFT             16

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RSVD_HW_INTR_MASK          0x0000ff80
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RSVD_HW_INTR_SHIFT         7

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_WATCHDOG_INTR_MASK         0x00000040
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_WATCHDOG_INTR_SHIFT        6

/* AVD_INTR2_0 :: CPU_STATUS :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_REG_INTR_MASK             0x00000020
#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_REG_INTR_SHIFT            5

/* AVD_INTR2_0 :: CPU_STATUS :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_SCB_WR_INTR_MASK          0x00000010
#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_SCB_WR_INTR_SHIFT         4

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_PFRI_INTR_MASK             0x00000008
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_PFRI_INTR_SHIFT            3

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_MBOX_INTR_MASK             0x00000004
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_MBOX_INTR_SHIFT            2

/* AVD_INTR2_0 :: CPU_STATUS :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_INST_RD_INTR_MASK         0x00000002
#define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_INST_RD_INTR_SHIFT        1

/* AVD_INTR2_0 :: CPU_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RGR_BRIDGE_INTR_MASK       0x00000001
#define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT      0

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR15_MASK                0x80000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR15_SHIFT               31

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR14_MASK                0x40000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR14_SHIFT               30

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR13_MASK                0x20000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR13_SHIFT               29

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR12_MASK                0x10000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR12_SHIFT               28

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR11_MASK                0x08000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR11_SHIFT               27

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR10_MASK                0x04000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR10_SHIFT               26

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR9_MASK                 0x02000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR9_SHIFT                25

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR8_MASK                 0x01000000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR8_SHIFT                24

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR7_MASK                 0x00800000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR7_SHIFT                23

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR6_MASK                 0x00400000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR6_SHIFT                22

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR5_MASK                 0x00200000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR5_SHIFT                21

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR4_MASK                 0x00100000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR4_SHIFT                20

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR3_MASK                 0x00080000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR3_SHIFT                19

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR2_MASK                 0x00040000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR2_SHIFT                18

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR1_MASK                 0x00020000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR1_SHIFT                17

/* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR0_MASK                 0x00010000
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR0_SHIFT                16

/* AVD_INTR2_0 :: CPU_SET :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RSVD_HW_INTR_MASK             0x0000ff80
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RSVD_HW_INTR_SHIFT            7

/* AVD_INTR2_0 :: CPU_SET :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_WATCHDOG_INTR_MASK            0x00000040
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_WATCHDOG_INTR_SHIFT           6

/* AVD_INTR2_0 :: CPU_SET :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_CPU_SET_VICH_REG_INTR_MASK                0x00000020
#define BCHP_AVD_INTR2_0_CPU_SET_VICH_REG_INTR_SHIFT               5

/* AVD_INTR2_0 :: CPU_SET :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_CPU_SET_VICH_SCB_WR_INTR_MASK             0x00000010
#define BCHP_AVD_INTR2_0_CPU_SET_VICH_SCB_WR_INTR_SHIFT            4

/* AVD_INTR2_0 :: CPU_SET :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_PFRI_INTR_MASK                0x00000008
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_PFRI_INTR_SHIFT               3

/* AVD_INTR2_0 :: CPU_SET :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_MBOX_INTR_MASK                0x00000004
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_MBOX_INTR_SHIFT               2

/* AVD_INTR2_0 :: CPU_SET :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_CPU_SET_VICH_INST_RD_INTR_MASK            0x00000002
#define BCHP_AVD_INTR2_0_CPU_SET_VICH_INST_RD_INTR_SHIFT           1

/* AVD_INTR2_0 :: CPU_SET :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RGR_BRIDGE_INTR_MASK          0x00000001
#define BCHP_AVD_INTR2_0_CPU_SET_AVD_RGR_BRIDGE_INTR_SHIFT         0

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR15_MASK              0x80000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR15_SHIFT             31

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR14_MASK              0x40000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR14_SHIFT             30

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR13_MASK              0x20000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR13_SHIFT             29

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR12_MASK              0x10000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR12_SHIFT             28

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR11_MASK              0x08000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR11_SHIFT             27

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR10_MASK              0x04000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR10_SHIFT             26

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR9_MASK               0x02000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR9_SHIFT              25

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR8_MASK               0x01000000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR8_SHIFT              24

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR7_MASK               0x00800000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR7_SHIFT              23

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR6_MASK               0x00400000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR6_SHIFT              22

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR5_MASK               0x00200000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR5_SHIFT              21

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR4_MASK               0x00100000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR4_SHIFT              20

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR3_MASK               0x00080000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR3_SHIFT              19

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR2_MASK               0x00040000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR2_SHIFT              18

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR1_MASK               0x00020000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR1_SHIFT              17

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR0_MASK               0x00010000
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR0_SHIFT              16

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RSVD_HW_INTR_MASK           0x0000ff80
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RSVD_HW_INTR_SHIFT          7

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_WATCHDOG_INTR_MASK          0x00000040
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_WATCHDOG_INTR_SHIFT         6

/* AVD_INTR2_0 :: CPU_CLEAR :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_REG_INTR_MASK              0x00000020
#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_REG_INTR_SHIFT             5

/* AVD_INTR2_0 :: CPU_CLEAR :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_SCB_WR_INTR_MASK           0x00000010
#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_SCB_WR_INTR_SHIFT          4

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_PFRI_INTR_MASK              0x00000008
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_PFRI_INTR_SHIFT             3

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_MBOX_INTR_MASK              0x00000004
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_MBOX_INTR_SHIFT             2

/* AVD_INTR2_0 :: CPU_CLEAR :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_INST_RD_INTR_MASK          0x00000002
#define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_INST_RD_INTR_SHIFT         1

/* AVD_INTR2_0 :: CPU_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RGR_BRIDGE_INTR_MASK        0x00000001
#define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT       0

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR15_MASK        0x80000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR15_SHIFT       31

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR14_MASK        0x40000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR14_SHIFT       30

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR13_MASK        0x20000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR13_SHIFT       29

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR12_MASK        0x10000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR12_SHIFT       28

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR11_MASK        0x08000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR11_SHIFT       27

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR10_MASK        0x04000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR10_SHIFT       26

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR9_MASK         0x02000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR9_SHIFT        25

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR8_MASK         0x01000000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR8_SHIFT        24

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR7_MASK         0x00800000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR7_SHIFT        23

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR6_MASK         0x00400000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR6_SHIFT        22

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR5_MASK         0x00200000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR5_SHIFT        21

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR4_MASK         0x00100000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR4_SHIFT        20

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR3_MASK         0x00080000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR3_SHIFT        19

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR2_MASK         0x00040000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR2_SHIFT        18

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR1_MASK         0x00020000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR1_SHIFT        17

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR0_MASK         0x00010000
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR0_SHIFT        16

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RSVD_HW_INTR_MASK     0x0000ff80
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RSVD_HW_INTR_SHIFT    7

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_WATCHDOG_INTR_MASK    0x00000040
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_WATCHDOG_INTR_SHIFT   6

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_REG_INTR_MASK        0x00000020
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_REG_INTR_SHIFT       5

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_SCB_WR_INTR_MASK     0x00000010
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_SCB_WR_INTR_SHIFT    4

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_PFRI_INTR_MASK        0x00000008
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_PFRI_INTR_SHIFT       3

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_MBOX_INTR_MASK        0x00000004
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_MBOX_INTR_SHIFT       2

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_INST_RD_INTR_MASK    0x00000002
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_INST_RD_INTR_SHIFT   1

/* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RGR_BRIDGE_INTR_MASK  0x00000001
#define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR15_MASK           0x80000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR15_SHIFT          31

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR14_MASK           0x40000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR14_SHIFT          30

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR13_MASK           0x20000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR13_SHIFT          29

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR12_MASK           0x10000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR12_SHIFT          28

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR11_MASK           0x08000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR11_SHIFT          27

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR10_MASK           0x04000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR10_SHIFT          26

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR9_MASK            0x02000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR9_SHIFT           25

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR8_MASK            0x01000000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR8_SHIFT           24

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR7_MASK            0x00800000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR7_SHIFT           23

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR6_MASK            0x00400000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR6_SHIFT           22

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR5_MASK            0x00200000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR5_SHIFT           21

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR4_MASK            0x00100000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR4_SHIFT           20

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR3_MASK            0x00080000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR3_SHIFT           19

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR2_MASK            0x00040000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR2_SHIFT           18

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR1_MASK            0x00020000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR1_SHIFT           17

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR0_MASK            0x00010000
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR0_SHIFT           16

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RSVD_HW_INTR_MASK        0x0000ff80
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RSVD_HW_INTR_SHIFT       7

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_WATCHDOG_INTR_MASK       0x00000040
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_WATCHDOG_INTR_SHIFT      6

/* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_REG_INTR_MASK           0x00000020
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_REG_INTR_SHIFT          5

/* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_SCB_WR_INTR_MASK        0x00000010
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_SCB_WR_INTR_SHIFT       4

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_PFRI_INTR_MASK           0x00000008
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_PFRI_INTR_SHIFT          3

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_MBOX_INTR_MASK           0x00000004
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_MBOX_INTR_SHIFT          2

/* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_INST_RD_INTR_MASK       0x00000002
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_INST_RD_INTR_SHIFT      1

/* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RGR_BRIDGE_INTR_MASK     0x00000001
#define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RGR_BRIDGE_INTR_SHIFT    0

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR15_MASK         0x80000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR15_SHIFT        31

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR14_MASK         0x40000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR14_SHIFT        30

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR13_MASK         0x20000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR13_SHIFT        29

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR12_MASK         0x10000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR12_SHIFT        28

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR11_MASK         0x08000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR11_SHIFT        27

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR10_MASK         0x04000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR10_SHIFT        26

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR9_MASK          0x02000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR9_SHIFT         25

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR8_MASK          0x01000000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR8_SHIFT         24

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR7_MASK          0x00800000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR7_SHIFT         23

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR6_MASK          0x00400000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR6_SHIFT         22

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR5_MASK          0x00200000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR5_SHIFT         21

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR4_MASK          0x00100000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR4_SHIFT         20

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR3_MASK          0x00080000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR3_SHIFT         19

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR2_MASK          0x00040000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR2_SHIFT         18

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR1_MASK          0x00020000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR1_SHIFT         17

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR0_MASK          0x00010000
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR0_SHIFT         16

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RSVD_HW_INTR_MASK      0x0000ff80
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RSVD_HW_INTR_SHIFT     7

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_WATCHDOG_INTR_MASK     0x00000040
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_WATCHDOG_INTR_SHIFT    6

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_REG_INTR_MASK         0x00000020
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_REG_INTR_SHIFT        5

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_SCB_WR_INTR_MASK      0x00000010
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_SCB_WR_INTR_SHIFT     4

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_PFRI_INTR_MASK         0x00000008
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_PFRI_INTR_SHIFT        3

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_MBOX_INTR_MASK         0x00000004
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_MBOX_INTR_SHIFT        2

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_INST_RD_INTR_MASK     0x00000002
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_INST_RD_INTR_SHIFT    1

/* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_MASK   0x00000001
#define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT  0

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR15_MASK             0x80000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR15_SHIFT            31

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR14_MASK             0x40000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR14_SHIFT            30

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR13_MASK             0x20000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR13_SHIFT            29

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR12_MASK             0x10000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR12_SHIFT            28

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR11_MASK             0x08000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR11_SHIFT            27

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR10_MASK             0x04000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR10_SHIFT            26

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR9_MASK              0x02000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR9_SHIFT             25

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR8_MASK              0x01000000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR8_SHIFT             24

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR7_MASK              0x00800000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR7_SHIFT             23

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR6_MASK              0x00400000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR6_SHIFT             22

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR5_MASK              0x00200000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR5_SHIFT             21

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR4_MASK              0x00100000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR4_SHIFT             20

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR3_MASK              0x00080000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR3_SHIFT             19

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR2_MASK              0x00040000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR2_SHIFT             18

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR1_MASK              0x00020000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR1_SHIFT             17

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR0_MASK              0x00010000
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR0_SHIFT             16

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RSVD_HW_INTR_MASK          0x0000ff80
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RSVD_HW_INTR_SHIFT         7

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_WATCHDOG_INTR_MASK         0x00000040
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_WATCHDOG_INTR_SHIFT        6

/* AVD_INTR2_0 :: PCI_STATUS :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_REG_INTR_MASK             0x00000020
#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_REG_INTR_SHIFT            5

/* AVD_INTR2_0 :: PCI_STATUS :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_SCB_WR_INTR_MASK          0x00000010
#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_SCB_WR_INTR_SHIFT         4

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_PFRI_INTR_MASK             0x00000008
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_PFRI_INTR_SHIFT            3

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_MBOX_INTR_MASK             0x00000004
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_MBOX_INTR_SHIFT            2

/* AVD_INTR2_0 :: PCI_STATUS :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_INST_RD_INTR_MASK         0x00000002
#define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_INST_RD_INTR_SHIFT        1

/* AVD_INTR2_0 :: PCI_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RGR_BRIDGE_INTR_MASK       0x00000001
#define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT      0

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR15_MASK                0x80000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR15_SHIFT               31

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR14_MASK                0x40000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR14_SHIFT               30

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR13_MASK                0x20000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR13_SHIFT               29

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR12_MASK                0x10000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR12_SHIFT               28

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR11_MASK                0x08000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR11_SHIFT               27

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR10_MASK                0x04000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR10_SHIFT               26

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR9_MASK                 0x02000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR9_SHIFT                25

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR8_MASK                 0x01000000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR8_SHIFT                24

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR7_MASK                 0x00800000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR7_SHIFT                23

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR6_MASK                 0x00400000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR6_SHIFT                22

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR5_MASK                 0x00200000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR5_SHIFT                21

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR4_MASK                 0x00100000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR4_SHIFT                20

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR3_MASK                 0x00080000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR3_SHIFT                19

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR2_MASK                 0x00040000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR2_SHIFT                18

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR1_MASK                 0x00020000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR1_SHIFT                17

/* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR0_MASK                 0x00010000
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR0_SHIFT                16

/* AVD_INTR2_0 :: PCI_SET :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RSVD_HW_INTR_MASK             0x0000ff80
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RSVD_HW_INTR_SHIFT            7

/* AVD_INTR2_0 :: PCI_SET :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_WATCHDOG_INTR_MASK            0x00000040
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_WATCHDOG_INTR_SHIFT           6

/* AVD_INTR2_0 :: PCI_SET :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_PCI_SET_VICH_REG_INTR_MASK                0x00000020
#define BCHP_AVD_INTR2_0_PCI_SET_VICH_REG_INTR_SHIFT               5

/* AVD_INTR2_0 :: PCI_SET :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_PCI_SET_VICH_SCB_WR_INTR_MASK             0x00000010
#define BCHP_AVD_INTR2_0_PCI_SET_VICH_SCB_WR_INTR_SHIFT            4

/* AVD_INTR2_0 :: PCI_SET :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_PFRI_INTR_MASK                0x00000008
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_PFRI_INTR_SHIFT               3

/* AVD_INTR2_0 :: PCI_SET :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_MBOX_INTR_MASK                0x00000004
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_MBOX_INTR_SHIFT               2

/* AVD_INTR2_0 :: PCI_SET :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_PCI_SET_VICH_INST_RD_INTR_MASK            0x00000002
#define BCHP_AVD_INTR2_0_PCI_SET_VICH_INST_RD_INTR_SHIFT           1

/* AVD_INTR2_0 :: PCI_SET :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RGR_BRIDGE_INTR_MASK          0x00000001
#define BCHP_AVD_INTR2_0_PCI_SET_AVD_RGR_BRIDGE_INTR_SHIFT         0

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR15_MASK              0x80000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR15_SHIFT             31

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR14_MASK              0x40000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR14_SHIFT             30

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR13_MASK              0x20000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR13_SHIFT             29

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR12_MASK              0x10000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR12_SHIFT             28

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR11_MASK              0x08000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR11_SHIFT             27

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR10_MASK              0x04000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR10_SHIFT             26

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR9_MASK               0x02000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR9_SHIFT              25

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR8_MASK               0x01000000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR8_SHIFT              24

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR7_MASK               0x00800000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR7_SHIFT              23

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR6_MASK               0x00400000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR6_SHIFT              22

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR5_MASK               0x00200000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR5_SHIFT              21

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR4_MASK               0x00100000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR4_SHIFT              20

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR3_MASK               0x00080000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR3_SHIFT              19

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR2_MASK               0x00040000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR2_SHIFT              18

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR1_MASK               0x00020000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR1_SHIFT              17

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR0_MASK               0x00010000
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR0_SHIFT              16

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RSVD_HW_INTR_MASK           0x0000ff80
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RSVD_HW_INTR_SHIFT          7

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_WATCHDOG_INTR_MASK          0x00000040
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_WATCHDOG_INTR_SHIFT         6

/* AVD_INTR2_0 :: PCI_CLEAR :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_REG_INTR_MASK              0x00000020
#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_REG_INTR_SHIFT             5

/* AVD_INTR2_0 :: PCI_CLEAR :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_SCB_WR_INTR_MASK           0x00000010
#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_SCB_WR_INTR_SHIFT          4

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_PFRI_INTR_MASK              0x00000008
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_PFRI_INTR_SHIFT             3

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_MBOX_INTR_MASK              0x00000004
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_MBOX_INTR_SHIFT             2

/* AVD_INTR2_0 :: PCI_CLEAR :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_INST_RD_INTR_MASK          0x00000002
#define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_INST_RD_INTR_SHIFT         1

/* AVD_INTR2_0 :: PCI_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RGR_BRIDGE_INTR_MASK        0x00000001
#define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT       0

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR15_MASK        0x80000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR15_SHIFT       31

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR14_MASK        0x40000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR14_SHIFT       30

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR13_MASK        0x20000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR13_SHIFT       29

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR12_MASK        0x10000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR12_SHIFT       28

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR11_MASK        0x08000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR11_SHIFT       27

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR10_MASK        0x04000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR10_SHIFT       26

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR9_MASK         0x02000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR9_SHIFT        25

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR8_MASK         0x01000000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR8_SHIFT        24

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR7_MASK         0x00800000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR7_SHIFT        23

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR6_MASK         0x00400000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR6_SHIFT        22

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR5_MASK         0x00200000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR5_SHIFT        21

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR4_MASK         0x00100000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR4_SHIFT        20

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR3_MASK         0x00080000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR3_SHIFT        19

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR2_MASK         0x00040000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR2_SHIFT        18

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR1_MASK         0x00020000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR1_SHIFT        17

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR0_MASK         0x00010000
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR0_SHIFT        16

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RSVD_HW_INTR_MASK     0x0000ff80
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RSVD_HW_INTR_SHIFT    7

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_WATCHDOG_INTR_MASK    0x00000040
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_WATCHDOG_INTR_SHIFT   6

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_REG_INTR_MASK        0x00000020
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_REG_INTR_SHIFT       5

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_SCB_WR_INTR_MASK     0x00000010
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_SCB_WR_INTR_SHIFT    4

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_PFRI_INTR_MASK        0x00000008
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_PFRI_INTR_SHIFT       3

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_MBOX_INTR_MASK        0x00000004
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_MBOX_INTR_SHIFT       2

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_INST_RD_INTR_MASK    0x00000002
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_INST_RD_INTR_SHIFT   1

/* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RGR_BRIDGE_INTR_MASK  0x00000001
#define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR15_MASK           0x80000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR15_SHIFT          31

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR14_MASK           0x40000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR14_SHIFT          30

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR13_MASK           0x20000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR13_SHIFT          29

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR12_MASK           0x10000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR12_SHIFT          28

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR11_MASK           0x08000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR11_SHIFT          27

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR10_MASK           0x04000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR10_SHIFT          26

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR9_MASK            0x02000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR9_SHIFT           25

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR8_MASK            0x01000000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR8_SHIFT           24

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR7_MASK            0x00800000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR7_SHIFT           23

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR6_MASK            0x00400000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR6_SHIFT           22

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR5_MASK            0x00200000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR5_SHIFT           21

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR4_MASK            0x00100000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR4_SHIFT           20

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR3_MASK            0x00080000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR3_SHIFT           19

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR2_MASK            0x00040000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR2_SHIFT           18

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR1_MASK            0x00020000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR1_SHIFT           17

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR0_MASK            0x00010000
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR0_SHIFT           16

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RSVD_HW_INTR_MASK        0x0000ff80
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RSVD_HW_INTR_SHIFT       7

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_WATCHDOG_INTR_MASK       0x00000040
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_WATCHDOG_INTR_SHIFT      6

/* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_REG_INTR_MASK           0x00000020
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_REG_INTR_SHIFT          5

/* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_SCB_WR_INTR_MASK        0x00000010
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_SCB_WR_INTR_SHIFT       4

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_PFRI_INTR_MASK           0x00000008
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_PFRI_INTR_SHIFT          3

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_MBOX_INTR_MASK           0x00000004
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_MBOX_INTR_SHIFT          2

/* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_INST_RD_INTR_MASK       0x00000002
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_INST_RD_INTR_SHIFT      1

/* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RGR_BRIDGE_INTR_MASK     0x00000001
#define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RGR_BRIDGE_INTR_SHIFT    0

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR15 [31:31] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR15_MASK         0x80000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR15_SHIFT        31

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR14 [30:30] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR14_MASK         0x40000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR14_SHIFT        30

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR13 [29:29] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR13_MASK         0x20000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR13_SHIFT        29

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR12 [28:28] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR12_MASK         0x10000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR12_SHIFT        28

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR11 [27:27] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR11_MASK         0x08000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR11_SHIFT        27

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR10 [26:26] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR10_MASK         0x04000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR10_SHIFT        26

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR9 [25:25] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR9_MASK          0x02000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR9_SHIFT         25

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR8 [24:24] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR8_MASK          0x01000000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR8_SHIFT         24

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR7 [23:23] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR7_MASK          0x00800000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR7_SHIFT         23

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR6 [22:22] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR6_MASK          0x00400000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR6_SHIFT         22

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR5 [21:21] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR5_MASK          0x00200000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR5_SHIFT         21

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR4 [20:20] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR4_MASK          0x00100000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR4_SHIFT         20

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR3 [19:19] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR3_MASK          0x00080000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR3_SHIFT         19

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR2 [18:18] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR2_MASK          0x00040000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR2_SHIFT         18

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR1 [17:17] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR1_MASK          0x00020000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR1_SHIFT         17

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR0 [16:16] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR0_MASK          0x00010000
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR0_SHIFT         16

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_RSVD_HW_INTR [15:07] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RSVD_HW_INTR_MASK      0x0000ff80
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RSVD_HW_INTR_SHIFT     7

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_WATCHDOG_INTR [06:06] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_WATCHDOG_INTR_MASK     0x00000040
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_WATCHDOG_INTR_SHIFT    6

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_REG_INTR [05:05] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_REG_INTR_MASK         0x00000020
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_REG_INTR_SHIFT        5

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_SCB_WR_INTR [04:04] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_SCB_WR_INTR_MASK      0x00000010
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_SCB_WR_INTR_SHIFT     4

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_PFRI_INTR [03:03] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_PFRI_INTR_MASK         0x00000008
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_PFRI_INTR_SHIFT        3

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_MBOX_INTR [02:02] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_MBOX_INTR_MASK         0x00000004
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_MBOX_INTR_SHIFT        2

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_INST_RD_INTR [01:01] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_INST_RD_INTR_MASK     0x00000002
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_INST_RD_INTR_SHIFT    1

/* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_MASK   0x00000001
#define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT  0

#endif /* #ifndef BCHP_AVD_INTR2_0_H__ */

/* End of File */
