/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_decode_ind_sdram_regs_0.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:04p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:43:26 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:04p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_DECODE_IND_SDRAM_REGS_0_H__
#define BCHP_DECODE_IND_SDRAM_REGS_0_H__

/***************************************************************************
 *DECODE_IND_SDRAM_REGS_0
 ***************************************************************************/
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC 0x00841000 /* REG_SDRAM_INC */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR 0x00841004 /* REG_SDRAM_ADDR */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA 0x00841008 /* REG_SDRAM_DATA */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG 0x00841010 /* REG_CPU_DBG */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT 0x00841014 /* REG_SDRAM_STAT */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END 0x0084107c /* REG_SDRAM_END */

/***************************************************************************
 *REG_SDRAM_INC - REG_SDRAM_INC
 ***************************************************************************/
/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_INC :: reserved0 [31:01] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_reserved0_MASK  0xfffffffe
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_reserved0_SHIFT 1

/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_INC :: Inc [00:00] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_Inc_MASK        0x00000001
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_Inc_SHIFT       0

/***************************************************************************
 *REG_SDRAM_ADDR - REG_SDRAM_ADDR
 ***************************************************************************/
/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_ADDR :: Addr [31:02] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_Addr_MASK      0xfffffffc
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_Addr_SHIFT     2

/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_ADDR :: reserved0 [01:00] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_reserved0_MASK 0x00000003
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_reserved0_SHIFT 0

/***************************************************************************
 *REG_SDRAM_DATA - REG_SDRAM_DATA
 ***************************************************************************/
/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_DATA :: Data [31:00] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA_Data_MASK      0xffffffff
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA_Data_SHIFT     0

/***************************************************************************
 *REG_CPU_DBG - REG_CPU_DBG
 ***************************************************************************/
/* DECODE_IND_SDRAM_REGS_0 :: REG_CPU_DBG :: reserved0 [31:01] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_reserved0_MASK    0xfffffffe
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_reserved0_SHIFT   1

/* DECODE_IND_SDRAM_REGS_0 :: REG_CPU_DBG :: Hst [00:00] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_Hst_MASK          0x00000001
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_Hst_SHIFT         0

/***************************************************************************
 *REG_SDRAM_STAT - REG_SDRAM_STAT
 ***************************************************************************/
/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_STAT :: reserved0 [31:00] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT_reserved0_MASK 0xffffffff
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT_reserved0_SHIFT 0

/***************************************************************************
 *REG_SDRAM_END - REG_SDRAM_END
 ***************************************************************************/
/* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_END :: reserved0 [31:00] */
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END_reserved0_MASK  0xffffffff
#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END_reserved0_SHIFT 0

#endif /* #ifndef BCHP_DECODE_IND_SDRAM_REGS_0_H__ */

/* End of File */
