/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_pri_arb_arc_l1_regs.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:14p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:14 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:14p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_PRI_ARB_ARC_L1_REGS_H__
#define BCHP_PRI_ARB_ARC_L1_REGS_H__

/***************************************************************************
 *PRI_ARB_ARC_L1_REGS - PRIMARY_ARB L1 (ARCs) Interrupt Registers
 ***************************************************************************/
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS  0x0040cf00 /* Interrupt Status Register */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS  0x0040cf04 /* Interrupt Status Register */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS 0x0040cf08 /* Interrupt Mask Status Register */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS 0x0040cf0c /* Interrupt Mask Status Register */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET 0x0040cf10 /* Interrupt Mask Set Register */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET 0x0040cf14 /* Interrupt Mask Set Register */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR 0x0040cf18 /* Interrupt Mask Clear Register */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR 0x0040cf1c /* Interrupt Mask Clear Register */

/***************************************************************************
 *INTR_W0_STATUS - Interrupt Status Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: reserved0 [31:05] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_reserved0_MASK     0xffffffe0
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_reserved0_SHIFT    5

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ALIAS_INTR [04:04] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ALIAS_INTR_MASK    0x00000010
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ALIAS_INTR_SHIFT   4

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH3_INTR [03:03] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH3_INTR_MASK    0x00000008
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH3_INTR_SHIFT   3

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH2_INTR [02:02] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH2_INTR_MASK    0x00000004
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH2_INTR_SHIFT   2

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH1_INTR [01:01] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH1_INTR_MASK    0x00000002
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH1_INTR_SHIFT   1

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH0_INTR [00:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH0_INTR_MASK    0x00000001
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH0_INTR_SHIFT   0

/***************************************************************************
 *INTR_W1_STATUS - Interrupt Status Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W1_STATUS :: reserved0 [31:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS_reserved0_MASK     0xffffffff
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS_reserved0_SHIFT    0

/***************************************************************************
 *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: reserved0 [31:05] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_reserved0_SHIFT 5

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ALIAS_MASK [04:04] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ALIAS_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ALIAS_MASK_SHIFT 4

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH3_MASK_MASK 0x00000008
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH3_MASK_SHIFT 3

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH2_MASK_MASK 0x00000004
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH2_MASK_SHIFT 2

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH1_MASK_MASK 0x00000002
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH1_MASK_SHIFT 1

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH0_MASK_MASK 0x00000001
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH0_MASK_SHIFT 0

/***************************************************************************
 *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_STATUS :: reserved0 [31:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS_reserved0_MASK 0xffffffff
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS_reserved0_SHIFT 0

/***************************************************************************
 *INTR_W0_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: reserved0 [31:05] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_reserved0_MASK   0xffffffe0
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_reserved0_SHIFT  5

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ALIAS_MASK [04:04] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ALIAS_MASK_MASK  0x00000010
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ALIAS_MASK_SHIFT 4

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH3_MASK_MASK  0x00000008
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH3_MASK_SHIFT 3

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH2_MASK_MASK  0x00000004
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH2_MASK_SHIFT 2

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH1_MASK_MASK  0x00000002
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH1_MASK_SHIFT 1

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH0_MASK_MASK  0x00000001
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH0_MASK_SHIFT 0

/***************************************************************************
 *INTR_W1_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_SET :: reserved0 [31:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET_reserved0_MASK   0xffffffff
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET_reserved0_SHIFT  0

/***************************************************************************
 *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: reserved0 [31:05] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_reserved0_MASK 0xffffffe0
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_reserved0_SHIFT 5

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ALIAS_MASK [04:04] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ALIAS_MASK_MASK 0x00000010
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ALIAS_MASK_SHIFT 4

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH3_MASK [03:03] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH3_MASK_MASK 0x00000008
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH3_MASK_SHIFT 3

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH2_MASK [02:02] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH2_MASK_MASK 0x00000004
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH2_MASK_SHIFT 2

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH1_MASK [01:01] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH1_MASK_MASK 0x00000002
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH1_MASK_SHIFT 1

/* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH0_MASK [00:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH0_MASK_MASK 0x00000001
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH0_MASK_SHIFT 0

/***************************************************************************
 *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_CLEAR :: reserved0 [31:00] */
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR_reserved0_MASK 0xffffffff
#define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR_reserved0_SHIFT 0

#endif /* #ifndef BCHP_PRI_ARB_ARC_L1_REGS_H__ */

/* End of File */
