/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_misc3.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:11p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:19 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:11p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_MISC3_H__
#define BCHP_MISC3_H__

/***************************************************************************
 *MISC3 - Registers for Reset, Options, DMA Checksums
 ***************************************************************************/
#define BCHP_MISC3_RESET_CTRL                    0x00502200 /* Reset Control Register */
#define BCHP_MISC3_RX_CHECKSUM                   0x0050220c /* Pixel Receive Checksum */
#define BCHP_MISC3_TX_CHECKSUM                   0x00502210 /* Transmit Checksum */
#define BCHP_MISC3_ECO_CTRL_CORE                 0x00502214 /* ECO Core Reset Control Register */
#define BCHP_MISC3_OPTIONS_CTRL                  0x00502218 /* PCIe Options Control Register */
#define BCHP_MISC3_SW_ARB_CTRL                   0x00502220 /* Software Arbitration Register */
#define BCHP_MISC3_HIF_RX_CHECKSUM               0x00502224 /* HIF Receive Checksum */
#define BCHP_MISC3_META_CHECKSUM                 0x00502228 /* Meta Data Checksum */
#define BCHP_MISC3_MEMORY_CTRL                   0x0050222c /* Memory Control Register */

/***************************************************************************
 *RESET_CTRL - Reset Control Register
 ***************************************************************************/
/* MISC3 :: RESET_CTRL :: reserved0 [31:09] */
#define BCHP_MISC3_RESET_CTRL_reserved0_MASK                       0xfffffe00
#define BCHP_MISC3_RESET_CTRL_reserved0_SHIFT                      9

/* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */
#define BCHP_MISC3_RESET_CTRL_PLL_RESET_MASK                       0x00000100
#define BCHP_MISC3_RESET_CTRL_PLL_RESET_SHIFT                      8

/* MISC3 :: RESET_CTRL :: reserved1 [07:03] */
#define BCHP_MISC3_RESET_CTRL_reserved1_MASK                       0x000000f8
#define BCHP_MISC3_RESET_CTRL_reserved1_SHIFT                      3

/* MISC3 :: RESET_CTRL :: LOW_POWER [02:02] */
#define BCHP_MISC3_RESET_CTRL_LOW_POWER_MASK                       0x00000004
#define BCHP_MISC3_RESET_CTRL_LOW_POWER_SHIFT                      2

/* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */
#define BCHP_MISC3_RESET_CTRL_POR_RESET_MASK                       0x00000002
#define BCHP_MISC3_RESET_CTRL_POR_RESET_SHIFT                      1

/* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */
#define BCHP_MISC3_RESET_CTRL_CORE_RESET_MASK                      0x00000001
#define BCHP_MISC3_RESET_CTRL_CORE_RESET_SHIFT                     0

/***************************************************************************
 *RX_CHECKSUM - Pixel Receive Checksum
 ***************************************************************************/
/* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */
#define BCHP_MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK                    0xffffffff
#define BCHP_MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT                   0

/***************************************************************************
 *TX_CHECKSUM - Transmit Checksum
 ***************************************************************************/
/* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */
#define BCHP_MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK                    0xffffffff
#define BCHP_MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT                   0

/***************************************************************************
 *ECO_CTRL_CORE - ECO Core Reset Control Register
 ***************************************************************************/
/* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */
#define BCHP_MISC3_ECO_CTRL_CORE_reserved0_MASK                    0xffff0000
#define BCHP_MISC3_ECO_CTRL_CORE_reserved0_SHIFT                   16

/* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */
#define BCHP_MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK               0x0000ffff
#define BCHP_MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT              0

/***************************************************************************
 *OPTIONS_CTRL - PCIe Options Control Register
 ***************************************************************************/
/* MISC3 :: OPTIONS_CTRL :: reserved0 [31:05] */
#define BCHP_MISC3_OPTIONS_CTRL_reserved0_MASK                     0xffffffe0
#define BCHP_MISC3_OPTIONS_CTRL_reserved0_SHIFT                    5

/* MISC3 :: OPTIONS_CTRL :: CQ39842_FIX_DISABLE [04:04] */
#define BCHP_MISC3_OPTIONS_CTRL_CQ39842_FIX_DISABLE_MASK           0x00000010
#define BCHP_MISC3_OPTIONS_CTRL_CQ39842_FIX_DISABLE_SHIFT          4

/* MISC3 :: OPTIONS_CTRL :: CQ35254_DISABLE [03:03] */
#define BCHP_MISC3_OPTIONS_CTRL_CQ35254_DISABLE_MASK               0x00000008
#define BCHP_MISC3_OPTIONS_CTRL_CQ35254_DISABLE_SHIFT              3

/* MISC3 :: OPTIONS_CTRL :: CQ31984_ENABLE_OPT2 [02:02] */
#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT2_MASK           0x00000004
#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT2_SHIFT          2

/* MISC3 :: OPTIONS_CTRL :: CQ31984_ENABLE_OPT1 [01:01] */
#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT1_MASK           0x00000002
#define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT1_SHIFT          1

/* MISC3 :: OPTIONS_CTRL :: CQ30674_DISABLE [00:00] */
#define BCHP_MISC3_OPTIONS_CTRL_CQ30674_DISABLE_MASK               0x00000001
#define BCHP_MISC3_OPTIONS_CTRL_CQ30674_DISABLE_SHIFT              0

/***************************************************************************
 *SW_ARB_CTRL - Software Arbitration Register
 ***************************************************************************/
/* MISC3 :: SW_ARB_CTRL :: reserved0 [31:08] */
#define BCHP_MISC3_SW_ARB_CTRL_reserved0_MASK                      0xffffff00
#define BCHP_MISC3_SW_ARB_CTRL_reserved0_SHIFT                     8

/* MISC3 :: SW_ARB_CTRL :: req1 [07:07] */
#define BCHP_MISC3_SW_ARB_CTRL_req1_MASK                           0x00000080
#define BCHP_MISC3_SW_ARB_CTRL_req1_SHIFT                          7

/* MISC3 :: SW_ARB_CTRL :: arb_won1 [06:06] */
#define BCHP_MISC3_SW_ARB_CTRL_arb_won1_MASK                       0x00000040
#define BCHP_MISC3_SW_ARB_CTRL_arb_won1_SHIFT                      6

/* MISC3 :: SW_ARB_CTRL :: reserved1 [05:04] */
#define BCHP_MISC3_SW_ARB_CTRL_reserved1_MASK                      0x00000030
#define BCHP_MISC3_SW_ARB_CTRL_reserved1_SHIFT                     4

/* MISC3 :: SW_ARB_CTRL :: req0 [03:03] */
#define BCHP_MISC3_SW_ARB_CTRL_req0_MASK                           0x00000008
#define BCHP_MISC3_SW_ARB_CTRL_req0_SHIFT                          3

/* MISC3 :: SW_ARB_CTRL :: arb_won0 [02:02] */
#define BCHP_MISC3_SW_ARB_CTRL_arb_won0_MASK                       0x00000004
#define BCHP_MISC3_SW_ARB_CTRL_arb_won0_SHIFT                      2

/* MISC3 :: SW_ARB_CTRL :: req_clr0 [01:01] */
#define BCHP_MISC3_SW_ARB_CTRL_req_clr0_MASK                       0x00000002
#define BCHP_MISC3_SW_ARB_CTRL_req_clr0_SHIFT                      1

/* MISC3 :: SW_ARB_CTRL :: req_set0 [00:00] */
#define BCHP_MISC3_SW_ARB_CTRL_req_set0_MASK                       0x00000001
#define BCHP_MISC3_SW_ARB_CTRL_req_set0_SHIFT                      0

/***************************************************************************
 *HIF_RX_CHECKSUM - HIF Receive Checksum
 ***************************************************************************/
/* MISC3 :: HIF_RX_CHECKSUM :: HIF_RX_CHECKSUM [31:00] */
#define BCHP_MISC3_HIF_RX_CHECKSUM_HIF_RX_CHECKSUM_MASK            0xffffffff
#define BCHP_MISC3_HIF_RX_CHECKSUM_HIF_RX_CHECKSUM_SHIFT           0

/***************************************************************************
 *META_CHECKSUM - Meta Data Checksum
 ***************************************************************************/
/* MISC3 :: META_CHECKSUM :: META_CHECKSUM [31:00] */
#define BCHP_MISC3_META_CHECKSUM_META_CHECKSUM_MASK                0xffffffff
#define BCHP_MISC3_META_CHECKSUM_META_CHECKSUM_SHIFT               0

/***************************************************************************
 *MEMORY_CTRL - Memory Control Register
 ***************************************************************************/
/* MISC3 :: MEMORY_CTRL :: reserved0 [31:06] */
#define BCHP_MISC3_MEMORY_CTRL_reserved0_MASK                      0xffffffc0
#define BCHP_MISC3_MEMORY_CTRL_reserved0_SHIFT                     6

/* MISC3 :: MEMORY_CTRL :: TM_DLL_RETRY [05:04] */
#define BCHP_MISC3_MEMORY_CTRL_TM_DLL_RETRY_MASK                   0x00000030
#define BCHP_MISC3_MEMORY_CTRL_TM_DLL_RETRY_SHIFT                  4

/* MISC3 :: MEMORY_CTRL :: TM_TXDMA_BUFFER [03:02] */
#define BCHP_MISC3_MEMORY_CTRL_TM_TXDMA_BUFFER_MASK                0x0000000c
#define BCHP_MISC3_MEMORY_CTRL_TM_TXDMA_BUFFER_SHIFT               2

/* MISC3 :: MEMORY_CTRL :: TM_BC_FIFO [01:00] */
#define BCHP_MISC3_MEMORY_CTRL_TM_BC_FIFO_MASK                     0x00000003
#define BCHP_MISC3_MEMORY_CTRL_TM_BC_FIFO_SHIFT                    0

#endif /* #ifndef BCHP_MISC3_H__ */

/* End of File */
