/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_xpt_xpu.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:28p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:07 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:28p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_XPT_XPU_H__
#define BCHP_XPT_XPU_H__

/***************************************************************************
 *XPT_XPU - XPT XPU Control Registers
 ***************************************************************************/
#define BCHP_XPT_XPU_TESTREG                     0x00220000 /* Test register - reserved */
#define BCHP_XPT_XPU_PSW                         0x00220004 /* Processor status word */
#define BCHP_XPT_XPU_PSWSH                       0x00220008 /* Processor status word shadow */
#define BCHP_XPT_XPU_SP                          0x00220010 /* Stack pointer */
#define BCHP_XPT_XPU_PC                          0x00220018 /* Program counter */
#define BCHP_XPT_XPU_STACK_0                     0x00220020 /* Stack 0 */
#define BCHP_XPT_XPU_STACK_1                     0x00220024 /* Stack 1 */
#define BCHP_XPT_XPU_STACK_2                     0x00220028 /* Stack 2 */
#define BCHP_XPT_XPU_STACK_3                     0x0022002c /* Stack 3 */
#define BCHP_XPT_XPU_REG_R0_R1                   0x00220030 /* Register pair r0/r1 */
#define BCHP_XPT_XPU_REG_R2_R3                   0x00220034 /* Register pair r2/r3 */
#define BCHP_XPT_XPU_REG_R4_R5                   0x00220038 /* Register pair r4/r5 */
#define BCHP_XPT_XPU_REG_R6_R7                   0x0022003c /* Register pair r6/r7 */
#define BCHP_XPT_XPU_REG_R8_R9                   0x00220040 /* Register pair r8/r9 */
#define BCHP_XPT_XPU_REG_R10_R11                 0x00220044 /* Register pair r10/r11 */
#define BCHP_XPT_XPU_REG_R12_R13                 0x00220048 /* Register pair r12/r13 */
#define BCHP_XPT_XPU_REG_R14_R15                 0x0022004c /* Register pair r14/r15 */

/***************************************************************************
 *TESTREG - Test register - reserved
 ***************************************************************************/
/* XPT_XPU :: TESTREG :: reserved0 [31:01] */
#define BCHP_XPT_XPU_TESTREG_reserved0_MASK                        0xfffffffe
#define BCHP_XPT_XPU_TESTREG_reserved0_SHIFT                       1

/* XPT_XPU :: TESTREG :: TESTBIT [00:00] */
#define BCHP_XPT_XPU_TESTREG_TESTBIT_MASK                          0x00000001
#define BCHP_XPT_XPU_TESTREG_TESTBIT_SHIFT                         0

/***************************************************************************
 *PSW - Processor status word
 ***************************************************************************/
/* XPT_XPU :: PSW :: reserved0 [31:11] */
#define BCHP_XPT_XPU_PSW_reserved0_MASK                            0xfffff800
#define BCHP_XPT_XPU_PSW_reserved0_SHIFT                           11

/* XPT_XPU :: PSW :: DFLAG [10:10] */
#define BCHP_XPT_XPU_PSW_DFLAG_MASK                                0x00000400
#define BCHP_XPT_XPU_PSW_DFLAG_SHIFT                               10

/* XPT_XPU :: PSW :: LFLAG [09:09] */
#define BCHP_XPT_XPU_PSW_LFLAG_MASK                                0x00000200
#define BCHP_XPT_XPU_PSW_LFLAG_SHIFT                               9

/* XPT_XPU :: PSW :: VFLAG [08:08] */
#define BCHP_XPT_XPU_PSW_VFLAG_MASK                                0x00000100
#define BCHP_XPT_XPU_PSW_VFLAG_SHIFT                               8

/* XPT_XPU :: PSW :: HFLAG [07:07] */
#define BCHP_XPT_XPU_PSW_HFLAG_MASK                                0x00000080
#define BCHP_XPT_XPU_PSW_HFLAG_SHIFT                               7

/* XPT_XPU :: PSW :: WFLAG [06:06] */
#define BCHP_XPT_XPU_PSW_WFLAG_MASK                                0x00000040
#define BCHP_XPT_XPU_PSW_WFLAG_SHIFT                               6

/* XPT_XPU :: PSW :: IFLAG [05:05] */
#define BCHP_XPT_XPU_PSW_IFLAG_MASK                                0x00000020
#define BCHP_XPT_XPU_PSW_IFLAG_SHIFT                               5

/* XPT_XPU :: PSW :: EFLAG [04:04] */
#define BCHP_XPT_XPU_PSW_EFLAG_MASK                                0x00000010
#define BCHP_XPT_XPU_PSW_EFLAG_SHIFT                               4

/* XPT_XPU :: PSW :: CFLAG [03:03] */
#define BCHP_XPT_XPU_PSW_CFLAG_MASK                                0x00000008
#define BCHP_XPT_XPU_PSW_CFLAG_SHIFT                               3

/* XPT_XPU :: PSW :: SFLAG [02:02] */
#define BCHP_XPT_XPU_PSW_SFLAG_MASK                                0x00000004
#define BCHP_XPT_XPU_PSW_SFLAG_SHIFT                               2

/* XPT_XPU :: PSW :: ZFLAG [01:01] */
#define BCHP_XPT_XPU_PSW_ZFLAG_MASK                                0x00000002
#define BCHP_XPT_XPU_PSW_ZFLAG_SHIFT                               1

/* XPT_XPU :: PSW :: OFLAG [00:00] */
#define BCHP_XPT_XPU_PSW_OFLAG_MASK                                0x00000001
#define BCHP_XPT_XPU_PSW_OFLAG_SHIFT                               0

/***************************************************************************
 *PSWSH - Processor status word shadow
 ***************************************************************************/
/* XPT_XPU :: PSWSH :: reserved0 [31:07] */
#define BCHP_XPT_XPU_PSWSH_reserved0_MASK                          0xffffff80
#define BCHP_XPT_XPU_PSWSH_reserved0_SHIFT                         7

/* XPT_XPU :: PSWSH :: WFLAG [06:06] */
#define BCHP_XPT_XPU_PSWSH_WFLAG_MASK                              0x00000040
#define BCHP_XPT_XPU_PSWSH_WFLAG_SHIFT                             6

/* XPT_XPU :: PSWSH :: reserved1 [05:04] */
#define BCHP_XPT_XPU_PSWSH_reserved1_MASK                          0x00000030
#define BCHP_XPT_XPU_PSWSH_reserved1_SHIFT                         4

/* XPT_XPU :: PSWSH :: CFLAG [03:03] */
#define BCHP_XPT_XPU_PSWSH_CFLAG_MASK                              0x00000008
#define BCHP_XPT_XPU_PSWSH_CFLAG_SHIFT                             3

/* XPT_XPU :: PSWSH :: SFLAG [02:02] */
#define BCHP_XPT_XPU_PSWSH_SFLAG_MASK                              0x00000004
#define BCHP_XPT_XPU_PSWSH_SFLAG_SHIFT                             2

/* XPT_XPU :: PSWSH :: ZFLAG [01:01] */
#define BCHP_XPT_XPU_PSWSH_ZFLAG_MASK                              0x00000002
#define BCHP_XPT_XPU_PSWSH_ZFLAG_SHIFT                             1

/* XPT_XPU :: PSWSH :: OFLAG [00:00] */
#define BCHP_XPT_XPU_PSWSH_OFLAG_MASK                              0x00000001
#define BCHP_XPT_XPU_PSWSH_OFLAG_SHIFT                             0

/***************************************************************************
 *SP - Stack pointer
 ***************************************************************************/
/* XPT_XPU :: SP :: reserved0 [31:02] */
#define BCHP_XPT_XPU_SP_reserved0_MASK                             0xfffffffc
#define BCHP_XPT_XPU_SP_reserved0_SHIFT                            2

/* XPT_XPU :: SP :: SPTR [01:00] */
#define BCHP_XPT_XPU_SP_SPTR_MASK                                  0x00000003
#define BCHP_XPT_XPU_SP_SPTR_SHIFT                                 0

/***************************************************************************
 *PC - Program counter
 ***************************************************************************/
/* XPT_XPU :: PC :: reserved0 [31:12] */
#define BCHP_XPT_XPU_PC_reserved0_MASK                             0xfffff000
#define BCHP_XPT_XPU_PC_reserved0_SHIFT                            12

/* XPT_XPU :: PC :: PC [11:00] */
#define BCHP_XPT_XPU_PC_PC_MASK                                    0x00000fff
#define BCHP_XPT_XPU_PC_PC_SHIFT                                   0

/***************************************************************************
 *STACK_0 - Stack 0
 ***************************************************************************/
/* XPT_XPU :: STACK_0 :: reserved0 [31:13] */
#define BCHP_XPT_XPU_STACK_0_reserved0_MASK                        0xffffe000
#define BCHP_XPT_XPU_STACK_0_reserved0_SHIFT                       13

/* XPT_XPU :: STACK_0 :: VALID [12:12] */
#define BCHP_XPT_XPU_STACK_0_VALID_MASK                            0x00001000
#define BCHP_XPT_XPU_STACK_0_VALID_SHIFT                           12

/* XPT_XPU :: STACK_0 :: STACK_DATA [11:00] */
#define BCHP_XPT_XPU_STACK_0_STACK_DATA_MASK                       0x00000fff
#define BCHP_XPT_XPU_STACK_0_STACK_DATA_SHIFT                      0

/***************************************************************************
 *STACK_1 - Stack 1
 ***************************************************************************/
/* XPT_XPU :: STACK_1 :: reserved0 [31:13] */
#define BCHP_XPT_XPU_STACK_1_reserved0_MASK                        0xffffe000
#define BCHP_XPT_XPU_STACK_1_reserved0_SHIFT                       13

/* XPT_XPU :: STACK_1 :: VALID [12:12] */
#define BCHP_XPT_XPU_STACK_1_VALID_MASK                            0x00001000
#define BCHP_XPT_XPU_STACK_1_VALID_SHIFT                           12

/* XPT_XPU :: STACK_1 :: STACK_DATA [11:00] */
#define BCHP_XPT_XPU_STACK_1_STACK_DATA_MASK                       0x00000fff
#define BCHP_XPT_XPU_STACK_1_STACK_DATA_SHIFT                      0

/***************************************************************************
 *STACK_2 - Stack 2
 ***************************************************************************/
/* XPT_XPU :: STACK_2 :: reserved0 [31:13] */
#define BCHP_XPT_XPU_STACK_2_reserved0_MASK                        0xffffe000
#define BCHP_XPT_XPU_STACK_2_reserved0_SHIFT                       13

/* XPT_XPU :: STACK_2 :: VALID [12:12] */
#define BCHP_XPT_XPU_STACK_2_VALID_MASK                            0x00001000
#define BCHP_XPT_XPU_STACK_2_VALID_SHIFT                           12

/* XPT_XPU :: STACK_2 :: STACK_DATA [11:00] */
#define BCHP_XPT_XPU_STACK_2_STACK_DATA_MASK                       0x00000fff
#define BCHP_XPT_XPU_STACK_2_STACK_DATA_SHIFT                      0

/***************************************************************************
 *STACK_3 - Stack 3
 ***************************************************************************/
/* XPT_XPU :: STACK_3 :: reserved0 [31:13] */
#define BCHP_XPT_XPU_STACK_3_reserved0_MASK                        0xffffe000
#define BCHP_XPT_XPU_STACK_3_reserved0_SHIFT                       13

/* XPT_XPU :: STACK_3 :: VALID [12:12] */
#define BCHP_XPT_XPU_STACK_3_VALID_MASK                            0x00001000
#define BCHP_XPT_XPU_STACK_3_VALID_SHIFT                           12

/* XPT_XPU :: STACK_3 :: STACK_DATA [11:00] */
#define BCHP_XPT_XPU_STACK_3_STACK_DATA_MASK                       0x00000fff
#define BCHP_XPT_XPU_STACK_3_STACK_DATA_SHIFT                      0

/***************************************************************************
 *REG_R0_R1 - Register pair r0/r1
 ***************************************************************************/
/* XPT_XPU :: REG_R0_R1 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R0_R1_reserved0_MASK                      0xffff0000
#define BCHP_XPT_XPU_REG_R0_R1_reserved0_SHIFT                     16

/* XPT_XPU :: REG_R0_R1 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R0_R1_REGISTER_MASK                       0x0000ffff
#define BCHP_XPT_XPU_REG_R0_R1_REGISTER_SHIFT                      0

/***************************************************************************
 *REG_R2_R3 - Register pair r2/r3
 ***************************************************************************/
/* XPT_XPU :: REG_R2_R3 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R2_R3_reserved0_MASK                      0xffff0000
#define BCHP_XPT_XPU_REG_R2_R3_reserved0_SHIFT                     16

/* XPT_XPU :: REG_R2_R3 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R2_R3_REGISTER_MASK                       0x0000ffff
#define BCHP_XPT_XPU_REG_R2_R3_REGISTER_SHIFT                      0

/***************************************************************************
 *REG_R4_R5 - Register pair r4/r5
 ***************************************************************************/
/* XPT_XPU :: REG_R4_R5 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R4_R5_reserved0_MASK                      0xffff0000
#define BCHP_XPT_XPU_REG_R4_R5_reserved0_SHIFT                     16

/* XPT_XPU :: REG_R4_R5 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R4_R5_REGISTER_MASK                       0x0000ffff
#define BCHP_XPT_XPU_REG_R4_R5_REGISTER_SHIFT                      0

/***************************************************************************
 *REG_R6_R7 - Register pair r6/r7
 ***************************************************************************/
/* XPT_XPU :: REG_R6_R7 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R6_R7_reserved0_MASK                      0xffff0000
#define BCHP_XPT_XPU_REG_R6_R7_reserved0_SHIFT                     16

/* XPT_XPU :: REG_R6_R7 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R6_R7_REGISTER_MASK                       0x0000ffff
#define BCHP_XPT_XPU_REG_R6_R7_REGISTER_SHIFT                      0

/***************************************************************************
 *REG_R8_R9 - Register pair r8/r9
 ***************************************************************************/
/* XPT_XPU :: REG_R8_R9 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R8_R9_reserved0_MASK                      0xffff0000
#define BCHP_XPT_XPU_REG_R8_R9_reserved0_SHIFT                     16

/* XPT_XPU :: REG_R8_R9 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R8_R9_REGISTER_MASK                       0x0000ffff
#define BCHP_XPT_XPU_REG_R8_R9_REGISTER_SHIFT                      0

/***************************************************************************
 *REG_R10_R11 - Register pair r10/r11
 ***************************************************************************/
/* XPT_XPU :: REG_R10_R11 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R10_R11_reserved0_MASK                    0xffff0000
#define BCHP_XPT_XPU_REG_R10_R11_reserved0_SHIFT                   16

/* XPT_XPU :: REG_R10_R11 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R10_R11_REGISTER_MASK                     0x0000ffff
#define BCHP_XPT_XPU_REG_R10_R11_REGISTER_SHIFT                    0

/***************************************************************************
 *REG_R12_R13 - Register pair r12/r13
 ***************************************************************************/
/* XPT_XPU :: REG_R12_R13 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R12_R13_reserved0_MASK                    0xffff0000
#define BCHP_XPT_XPU_REG_R12_R13_reserved0_SHIFT                   16

/* XPT_XPU :: REG_R12_R13 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R12_R13_REGISTER_MASK                     0x0000ffff
#define BCHP_XPT_XPU_REG_R12_R13_REGISTER_SHIFT                    0

/***************************************************************************
 *REG_R14_R15 - Register pair r14/r15
 ***************************************************************************/
/* XPT_XPU :: REG_R14_R15 :: reserved0 [31:16] */
#define BCHP_XPT_XPU_REG_R14_R15_reserved0_MASK                    0xffff0000
#define BCHP_XPT_XPU_REG_R14_R15_reserved0_SHIFT                   16

/* XPT_XPU :: REG_R14_R15 :: REGISTER [15:00] */
#define BCHP_XPT_XPU_REG_R14_R15_REGISTER_MASK                     0x0000ffff
#define BCHP_XPT_XPU_REG_R14_R15_REGISTER_SHIFT                    0

/***************************************************************************
 *IMEM%i - Instruction memory address 0..2047
 ***************************************************************************/
#define BCHP_XPT_XPU_IMEMi_ARRAY_BASE                              0x00220800
#define BCHP_XPT_XPU_IMEMi_ARRAY_START                             0
#define BCHP_XPT_XPU_IMEMi_ARRAY_END                               2047
#define BCHP_XPT_XPU_IMEMi_ARRAY_ELEMENT_SIZE                      32

/***************************************************************************
 *IMEM%i - Instruction memory address 0..2047
 ***************************************************************************/
/* XPT_XPU :: IMEMi :: reserved0 [31:22] */
#define BCHP_XPT_XPU_IMEMi_reserved0_MASK                          0xffc00000
#define BCHP_XPT_XPU_IMEMi_reserved0_SHIFT                         22

/* XPT_XPU :: IMEMi :: INSTRUCTION [21:00] */
#define BCHP_XPT_XPU_IMEMi_INSTRUCTION_MASK                        0x003fffff
#define BCHP_XPT_XPU_IMEMi_INSTRUCTION_SHIFT                       0


#endif /* #ifndef BCHP_XPT_XPU_H__ */

/* End of File */
