/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_xpt_rave.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:26p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:27 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:26p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_XPT_RAVE_H__
#define BCHP_XPT_RAVE_H__

/***************************************************************************
 *XPT_RAVE - XPT RAV Control Registers
 ***************************************************************************/
#define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR       0x00210000 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR        0x00210004 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR        0x00210008 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR         0x0021000c /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR       0x00210010 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR  0x00210014 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL 0x00210018 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH           0x0021001c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS          0x00210020 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR       0x00210024 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR        0x00210028 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR        0x0021002c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR         0x00210030 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR       0x00210034 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR  0x00210038 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL 0x0021003c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH           0x00210040 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG        0x00210044 /* Context 0 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB        0x00210048 /* Context 0 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD        0x0021004c /* Context 0 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF        0x00210050 /* Context 0 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH        0x00210054 /* Context 0 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1        0x00210058 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2        0x0021005c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3        0x00210060 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES   0x00210064 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL       0x00210068 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL   0x0021006c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL      0x00210070 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL    0x00210074 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL 0x00210078 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL       0x0021007c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL   0x00210080 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL      0x00210084 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL    0x00210088 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL 0x0021008c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode  0x00210090 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID       0x00210094 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1              0x00210098 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX0_REC_INIT_TS            0x0021009c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL            0x002100a0 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG        0x002100a4 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4        0x002100a8 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX0_PIC_CTR                0x002100ac /* Picture Counter register */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE           0x002100b0 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX0_REC_TIMER              0x002100b4 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX0_REC_STATE0             0x002100b8 /* Record State Register */
#define BCHP_XPT_RAVE_CX0_REC_STATE1             0x002100bc /* Record State Register */
#define BCHP_XPT_RAVE_CX0_REC_STATE2             0x002100c0 /* Record State Register */
#define BCHP_XPT_RAVE_CX0_REC_STATE2b            0x002100c4 /* Record State Register */
#define BCHP_XPT_RAVE_CX0_REC_STATE3             0x002100c8 /* Record State Register */
#define BCHP_XPT_RAVE_CX0_REC_COUNT              0x002100cc /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL       0x002100d0 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1     0x002100d4 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_0             0x002100d8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_1             0x002100dc /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_2             0x002100e0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_3             0x002100e4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR       0x002100e8 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR        0x002100ec /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR        0x002100f0 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR         0x002100f4 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR       0x002100f8 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR  0x002100fc /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL 0x00210100 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH           0x00210104 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS          0x00210108 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR       0x0021010c /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR        0x00210110 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR        0x00210114 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR         0x00210118 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR       0x0021011c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR  0x00210120 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL 0x00210124 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH           0x00210128 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG        0x0021012c /* Context 1 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB        0x00210130 /* Context 1 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD        0x00210134 /* Context 1 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF        0x00210138 /* Context 1 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH        0x0021013c /* Context 1 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1        0x00210140 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2        0x00210144 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3        0x00210148 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES   0x0021014c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL       0x00210150 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL   0x00210154 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL      0x00210158 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL    0x0021015c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL 0x00210160 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL       0x00210164 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL   0x00210168 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL      0x0021016c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL    0x00210170 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL 0x00210174 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE  0x00210178 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID       0x0021017c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1              0x00210180 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX1_REC_INIT_TS            0x00210184 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL            0x00210188 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG        0x0021018c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4        0x00210190 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX1_PIC_CTR                0x00210194 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE           0x00210198 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX1_REC_TIMER              0x0021019c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX1_REC_STATE0             0x002101a0 /* Record State Register */
#define BCHP_XPT_RAVE_CX1_REC_STATE1             0x002101a4 /* Record State Register */
#define BCHP_XPT_RAVE_CX1_REC_STATE2             0x002101a8 /* Record State Register */
#define BCHP_XPT_RAVE_CX1_REC_STATE2b            0x002101ac /* Record State Register */
#define BCHP_XPT_RAVE_CX1_REC_STATE3             0x002101b0 /* Record State Register */
#define BCHP_XPT_RAVE_CX1_REC_COUNT              0x002101b4 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL       0x002101b8 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1     0x002101bc /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_0             0x002101c0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_1             0x002101c4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_2             0x002101c8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_3             0x002101cc /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR       0x002101d0 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR        0x002101d4 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR        0x002101d8 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR         0x002101dc /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR       0x002101e0 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR  0x002101e4 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL 0x002101e8 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH           0x002101ec /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS          0x002101f0 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR       0x002101f4 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR        0x002101f8 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR        0x002101fc /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR         0x00210200 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR       0x00210204 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR  0x00210208 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL 0x0021020c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH           0x00210210 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG        0x00210214 /* Context 2 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB        0x00210218 /* Context 2 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD        0x0021021c /* Context 2 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF        0x00210220 /* Context 2 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH        0x00210224 /* Context 2 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1        0x00210228 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2        0x0021022c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3        0x00210230 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES   0x00210234 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL       0x00210238 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL   0x0021023c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL      0x00210240 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL    0x00210244 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL 0x00210248 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL       0x0021024c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL   0x00210250 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL      0x00210254 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL    0x00210258 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL 0x0021025c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode  0x00210260 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID       0x00210264 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1              0x00210268 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX2_REC_INIT_TS            0x0021026c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL            0x00210270 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG        0x00210274 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4        0x00210278 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX2_PIC_CTR                0x0021027c /* Picture Counter register */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE           0x00210280 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX2_REC_TIMER              0x00210284 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX2_REC_STATE0             0x00210288 /* Record State Register */
#define BCHP_XPT_RAVE_CX2_REC_STATE1             0x0021028c /* Record State Register */
#define BCHP_XPT_RAVE_CX2_REC_STATE2             0x00210290 /* Record State Register */
#define BCHP_XPT_RAVE_CX2_REC_STATE2b            0x00210294 /* Record State Register */
#define BCHP_XPT_RAVE_CX2_REC_STATE3             0x00210298 /* Record State Register */
#define BCHP_XPT_RAVE_CX2_REC_COUNT              0x0021029c /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL       0x002102a0 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1     0x002102a4 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_0             0x002102a8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_1             0x002102ac /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_2             0x002102b0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_3             0x002102b4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR       0x002102b8 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR        0x002102bc /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR        0x002102c0 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR         0x002102c4 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR       0x002102c8 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR  0x002102cc /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL 0x002102d0 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH           0x002102d4 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS          0x002102d8 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR       0x002102dc /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR        0x002102e0 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR        0x002102e4 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR         0x002102e8 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR       0x002102ec /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR  0x002102f0 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL 0x002102f4 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH           0x002102f8 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG        0x002102fc /* Context 3 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB        0x00210300 /* Context 3 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD        0x00210304 /* Context 3 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF        0x00210308 /* Context 3 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH        0x0021030c /* Context 3 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1        0x00210310 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2        0x00210314 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3        0x00210318 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES   0x0021031c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL       0x00210320 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL   0x00210324 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL      0x00210328 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL    0x0021032c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL 0x00210330 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL       0x00210334 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL   0x00210338 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL      0x0021033c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL    0x00210340 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL 0x00210344 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode  0x00210348 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID       0x0021034c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1              0x00210350 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX3_REC_INIT_TS            0x00210354 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL            0x00210358 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG        0x0021035c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4        0x00210360 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX3_PIC_CTR                0x00210364 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE           0x00210368 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX3_REC_TIMER              0x0021036c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX3_REC_STATE0             0x00210370 /* Record State Register */
#define BCHP_XPT_RAVE_CX3_REC_STATE1             0x00210374 /* Record State Register */
#define BCHP_XPT_RAVE_CX3_REC_STATE2             0x00210378 /* Record State Register */
#define BCHP_XPT_RAVE_CX3_REC_STATE2b            0x0021037c /* Record State Register */
#define BCHP_XPT_RAVE_CX3_REC_STATE3             0x00210380 /* Record State Register */
#define BCHP_XPT_RAVE_CX3_REC_COUNT              0x00210384 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL       0x00210388 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1     0x0021038c /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_0             0x00210390 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_1             0x00210394 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_2             0x00210398 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_3             0x0021039c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR       0x002103a0 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR        0x002103a4 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR        0x002103a8 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR         0x002103ac /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR       0x002103b0 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR  0x002103b4 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL 0x002103b8 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH           0x002103bc /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS          0x002103c0 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR       0x002103c4 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR        0x002103c8 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR        0x002103cc /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR         0x002103d0 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR       0x002103d4 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR  0x002103d8 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL 0x002103dc /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH           0x002103e0 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG        0x002103e4 /* Context 4 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB        0x002103e8 /* Context 4 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD        0x002103ec /* Context 4 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF        0x002103f0 /* Context 4 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH        0x002103f4 /* Context 4 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1        0x002103f8 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2        0x002103fc /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3        0x00210400 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES   0x00210404 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL       0x00210408 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL   0x0021040c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL      0x00210410 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL    0x00210414 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL 0x00210418 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL       0x0021041c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL   0x00210420 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL      0x00210424 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL    0x00210428 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL 0x0021042c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode  0x00210430 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID       0x00210434 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1              0x00210438 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX4_REC_INIT_TS            0x0021043c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL            0x00210440 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG        0x00210444 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4        0x00210448 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX4_PIC_CTR                0x0021044c /* Picture Counter register */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE           0x00210450 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX4_REC_TIMER              0x00210454 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX4_REC_STATE0             0x00210458 /* Record State Register */
#define BCHP_XPT_RAVE_CX4_REC_STATE1             0x0021045c /* Record State Register */
#define BCHP_XPT_RAVE_CX4_REC_STATE2             0x00210460 /* Record State Register */
#define BCHP_XPT_RAVE_CX4_REC_STATE2b            0x00210464 /* Record State Register */
#define BCHP_XPT_RAVE_CX4_REC_STATE3             0x00210468 /* Record State Register */
#define BCHP_XPT_RAVE_CX4_REC_COUNT              0x0021046c /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL       0x00210470 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1     0x00210474 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_0             0x00210478 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_1             0x0021047c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_2             0x00210480 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_3             0x00210484 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR       0x00210488 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR        0x0021048c /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR        0x00210490 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR         0x00210494 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR       0x00210498 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR  0x0021049c /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL 0x002104a0 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH           0x002104a4 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS          0x002104a8 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR       0x002104ac /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR        0x002104b0 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR        0x002104b4 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR         0x002104b8 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR       0x002104bc /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR  0x002104c0 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL 0x002104c4 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH           0x002104c8 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG        0x002104cc /* Context 5 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB        0x002104d0 /* Context 5 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD        0x002104d4 /* Context 5 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF        0x002104d8 /* Context 5 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH        0x002104dc /* Context 5 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1        0x002104e0 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2        0x002104e4 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3        0x002104e8 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES   0x002104ec /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL       0x002104f0 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL   0x002104f4 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL      0x002104f8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL    0x002104fc /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL 0x00210500 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL       0x00210504 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL   0x00210508 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL      0x0021050c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL    0x00210510 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL 0x00210514 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE  0x00210518 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID       0x0021051c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1              0x00210520 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX5_REC_INIT_TS            0x00210524 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL            0x00210528 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG        0x0021052c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4        0x00210530 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX5_PIC_CTR                0x00210534 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE           0x00210538 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX5_REC_TIMER              0x0021053c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX5_REC_STATE0             0x00210540 /* Record State Register */
#define BCHP_XPT_RAVE_CX5_REC_STATE1             0x00210544 /* Record State Register */
#define BCHP_XPT_RAVE_CX5_REC_STATE2             0x00210548 /* Record State Register */
#define BCHP_XPT_RAVE_CX5_REC_STATE2b            0x0021054c /* Record State Register */
#define BCHP_XPT_RAVE_CX5_REC_STATE3             0x00210550 /* Record State Register */
#define BCHP_XPT_RAVE_CX5_REC_COUNT              0x00210554 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL       0x00210558 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1     0x0021055c /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_0             0x00210560 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_1             0x00210564 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_2             0x00210568 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_3             0x0021056c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR       0x00210570 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR        0x00210574 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR        0x00210578 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR         0x0021057c /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR       0x00210580 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR  0x00210584 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL 0x00210588 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH           0x0021058c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS          0x00210590 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR       0x00210594 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR        0x00210598 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR        0x0021059c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR         0x002105a0 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR       0x002105a4 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR  0x002105a8 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL 0x002105ac /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH           0x002105b0 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG        0x002105b4 /* Context 6 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB        0x002105b8 /* Context 6 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD        0x002105bc /* Context 6 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF        0x002105c0 /* Context 6 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH        0x002105c4 /* Context 6 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1        0x002105c8 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2        0x002105cc /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3        0x002105d0 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES   0x002105d4 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL       0x002105d8 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL   0x002105dc /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL      0x002105e0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL    0x002105e4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL 0x002105e8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL       0x002105ec /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL   0x002105f0 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL      0x002105f4 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL    0x002105f8 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL 0x002105fc /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode  0x00210600 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID       0x00210604 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1              0x00210608 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX6_REC_INIT_TS            0x0021060c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL            0x00210610 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG        0x00210614 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4        0x00210618 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX6_PIC_CTR                0x0021061c /* Picture Counter register */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE           0x00210620 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX6_REC_TIMER              0x00210624 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX6_REC_STATE0             0x00210628 /* Record State Register */
#define BCHP_XPT_RAVE_CX6_REC_STATE1             0x0021062c /* Record State Register */
#define BCHP_XPT_RAVE_CX6_REC_STATE2             0x00210630 /* Record State Register */
#define BCHP_XPT_RAVE_CX6_REC_STATE2b            0x00210634 /* Record State Register */
#define BCHP_XPT_RAVE_CX6_REC_STATE3             0x00210638 /* Record State Register */
#define BCHP_XPT_RAVE_CX6_REC_COUNT              0x0021063c /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL       0x00210640 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1     0x00210644 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_0             0x00210648 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_1             0x0021064c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_2             0x00210650 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_3             0x00210654 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR       0x00210658 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR        0x0021065c /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR        0x00210660 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR         0x00210664 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR       0x00210668 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR  0x0021066c /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL 0x00210670 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH           0x00210674 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS          0x00210678 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR       0x0021067c /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR        0x00210680 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR        0x00210684 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR         0x00210688 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR       0x0021068c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR  0x00210690 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL 0x00210694 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH           0x00210698 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG        0x0021069c /* Context 7 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB        0x002106a0 /* Context 7 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD        0x002106a4 /* Context 7 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF        0x002106a8 /* Context 7 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH        0x002106ac /* Context 7 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1        0x002106b0 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2        0x002106b4 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3        0x002106b8 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES   0x002106bc /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL       0x002106c0 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL   0x002106c4 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL      0x002106c8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL    0x002106cc /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL 0x002106d0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL       0x002106d4 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL   0x002106d8 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL      0x002106dc /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL    0x002106e0 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL 0x002106e4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE  0x002106e8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID       0x002106ec /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1              0x002106f0 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX7_REC_INIT_TS            0x002106f4 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL            0x002106f8 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG        0x002106fc /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4        0x00210700 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX7_PIC_CTR                0x00210704 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE           0x00210708 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX7_REC_TIMER              0x0021070c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX7_REC_STATE0             0x00210710 /* Record State Register */
#define BCHP_XPT_RAVE_CX7_REC_STATE1             0x00210714 /* Record State Register */
#define BCHP_XPT_RAVE_CX7_REC_STATE2             0x00210718 /* Record State Register */
#define BCHP_XPT_RAVE_CX7_REC_STATE2b            0x0021071c /* Record State Register */
#define BCHP_XPT_RAVE_CX7_REC_STATE3             0x00210720 /* Record State Register */
#define BCHP_XPT_RAVE_CX7_REC_COUNT              0x00210724 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL       0x00210728 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1     0x0021072c /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_0             0x00210730 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_1             0x00210734 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_2             0x00210738 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_3             0x0021073c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR       0x00210740 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR        0x00210744 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR        0x00210748 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR         0x0021074c /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR       0x00210750 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR  0x00210754 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL 0x00210758 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH           0x0021075c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS          0x00210760 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR       0x00210764 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR        0x00210768 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR        0x0021076c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR         0x00210770 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR       0x00210774 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR  0x00210778 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL 0x0021077c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH           0x00210780 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG        0x00210784 /* Context 8 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB        0x00210788 /* Context 8 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD        0x0021078c /* Context 8 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF        0x00210790 /* Context 8 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH        0x00210794 /* Context 8 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1        0x00210798 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2        0x0021079c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3        0x002107a0 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES   0x002107a4 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL       0x002107a8 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL   0x002107ac /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL      0x002107b0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL    0x002107b4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL 0x002107b8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL       0x002107bc /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL   0x002107c0 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL      0x002107c4 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL    0x002107c8 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL 0x002107cc /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode  0x002107d0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID       0x002107d4 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1              0x002107d8 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX8_REC_INIT_TS            0x002107dc /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL            0x002107e0 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG        0x002107e4 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4        0x002107e8 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX8_PIC_CTR                0x002107ec /* Picture Counter register */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE           0x002107f0 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX8_REC_TIMER              0x002107f4 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX8_REC_STATE0             0x002107f8 /* Record State Register */
#define BCHP_XPT_RAVE_CX8_REC_STATE1             0x002107fc /* Record State Register */
#define BCHP_XPT_RAVE_CX8_REC_STATE2             0x00210800 /* Record State Register */
#define BCHP_XPT_RAVE_CX8_REC_STATE2b            0x00210804 /* Record State Register */
#define BCHP_XPT_RAVE_CX8_REC_STATE3             0x00210808 /* Record State Register */
#define BCHP_XPT_RAVE_CX8_REC_COUNT              0x0021080c /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL       0x00210810 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1     0x00210814 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_0             0x00210818 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_1             0x0021081c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_2             0x00210820 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_3             0x00210824 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR       0x00210828 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR        0x0021082c /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR        0x00210830 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR         0x00210834 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR       0x00210838 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR  0x0021083c /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL 0x00210840 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH           0x00210844 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS          0x00210848 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR       0x0021084c /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR        0x00210850 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR        0x00210854 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR         0x00210858 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR       0x0021085c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR  0x00210860 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL 0x00210864 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH           0x00210868 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG        0x0021086c /* Context 9 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB        0x00210870 /* Context 9 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD        0x00210874 /* Context 9 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF        0x00210878 /* Context 9 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH        0x0021087c /* Context 9 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1        0x00210880 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2        0x00210884 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3        0x00210888 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES   0x0021088c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL       0x00210890 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL   0x00210894 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL      0x00210898 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL    0x0021089c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL 0x002108a0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL       0x002108a4 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL   0x002108a8 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL      0x002108ac /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL    0x002108b0 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL 0x002108b4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode  0x002108b8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID       0x002108bc /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1              0x002108c0 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX9_REC_INIT_TS            0x002108c4 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL            0x002108c8 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG        0x002108cc /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4        0x002108d0 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX9_PIC_CTR                0x002108d4 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE           0x002108d8 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX9_REC_TIMER              0x002108dc /* Record Timer Register */
#define BCHP_XPT_RAVE_CX9_REC_STATE0             0x002108e0 /* Record State Register */
#define BCHP_XPT_RAVE_CX9_REC_STATE1             0x002108e4 /* Record State Register */
#define BCHP_XPT_RAVE_CX9_REC_STATE2             0x002108e8 /* Record State Register */
#define BCHP_XPT_RAVE_CX9_REC_STATE2b            0x002108ec /* Record State Register */
#define BCHP_XPT_RAVE_CX9_REC_STATE3             0x002108f0 /* Record State Register */
#define BCHP_XPT_RAVE_CX9_REC_COUNT              0x002108f4 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL       0x002108f8 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1     0x002108fc /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_0             0x00210900 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_1             0x00210904 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_2             0x00210908 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_3             0x0021090c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR      0x00210910 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR       0x00210914 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR       0x00210918 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR        0x0021091c /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR      0x00210920 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR 0x00210924 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL 0x00210928 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH          0x0021092c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS         0x00210930 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR      0x00210934 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR       0x00210938 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR       0x0021093c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR        0x00210940 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR      0x00210944 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR 0x00210948 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL 0x0021094c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH          0x00210950 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG       0x00210954 /* Context 10 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB       0x00210958 /* Context 10 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD       0x0021095c /* Context 10 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF       0x00210960 /* Context 10 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH       0x00210964 /* Context 10 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1       0x00210968 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2       0x0021096c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3       0x00210970 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES  0x00210974 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL      0x00210978 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL  0x0021097c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL     0x00210980 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL   0x00210984 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL 0x00210988 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL      0x0021098c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL  0x00210990 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL     0x00210994 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL   0x00210998 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL 0x0021099c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE 0x002109a0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID      0x002109a4 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1             0x002109a8 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX10_REC_INIT_TS           0x002109ac /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL           0x002109b0 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG       0x002109b4 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4       0x002109b8 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX10_PIC_CTR               0x002109bc /* Picture Counter register */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE          0x002109c0 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX10_REC_TIMER             0x002109c4 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX10_REC_STATE0            0x002109c8 /* Record State Register */
#define BCHP_XPT_RAVE_CX10_REC_STATE1            0x002109cc /* Record State Register */
#define BCHP_XPT_RAVE_CX10_REC_STATE2            0x002109d0 /* Record State Register */
#define BCHP_XPT_RAVE_CX10_REC_STATE2b           0x002109d4 /* Record State Register */
#define BCHP_XPT_RAVE_CX10_REC_STATE3            0x002109d8 /* Record State Register */
#define BCHP_XPT_RAVE_CX10_REC_COUNT             0x002109dc /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL      0x002109e0 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1    0x002109e4 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_0            0x002109e8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_1            0x002109ec /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_2            0x002109f0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_3            0x002109f4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR      0x002109f8 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR       0x002109fc /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR       0x00210a00 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR        0x00210a04 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR      0x00210a08 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR 0x00210a0c /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL 0x00210a10 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH          0x00210a14 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS         0x00210a18 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR      0x00210a1c /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR       0x00210a20 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR       0x00210a24 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR        0x00210a28 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR      0x00210a2c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR 0x00210a30 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL 0x00210a34 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH          0x00210a38 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG       0x00210a3c /* Context 11 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB       0x00210a40 /* Context 11 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD       0x00210a44 /* Context 11 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF       0x00210a48 /* Context 11 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH       0x00210a4c /* Context 11 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1       0x00210a50 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2       0x00210a54 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3       0x00210a58 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES  0x00210a5c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL      0x00210a60 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL  0x00210a64 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL     0x00210a68 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL   0x00210a6c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL 0x00210a70 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL      0x00210a74 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL  0x00210a78 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL     0x00210a7c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL   0x00210a80 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL 0x00210a84 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE 0x00210a88 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID      0x00210a8c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1             0x00210a90 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX11_REC_INIT_TS           0x00210a94 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL           0x00210a98 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG       0x00210a9c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4       0x00210aa0 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX11_PIC_CTR               0x00210aa4 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE          0x00210aa8 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX11_REC_TIMER             0x00210aac /* Record Timer Register */
#define BCHP_XPT_RAVE_CX11_REC_STATE0            0x00210ab0 /* Record State Register */
#define BCHP_XPT_RAVE_CX11_REC_STATE1            0x00210ab4 /* Record State Register */
#define BCHP_XPT_RAVE_CX11_REC_STATE2            0x00210ab8 /* Record State Register */
#define BCHP_XPT_RAVE_CX11_REC_STATE2b           0x00210abc /* Record State Register */
#define BCHP_XPT_RAVE_CX11_REC_STATE3            0x00210ac0 /* Record State Register */
#define BCHP_XPT_RAVE_CX11_REC_COUNT             0x00210ac4 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL      0x00210ac8 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1    0x00210acc /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_0            0x00210ad0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_1            0x00210ad4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_2            0x00210ad8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_3            0x00210adc /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR      0x00210ae0 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR       0x00210ae4 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR       0x00210ae8 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR        0x00210aec /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR      0x00210af0 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR 0x00210af4 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL 0x00210af8 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH          0x00210afc /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS         0x00210b00 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR      0x00210b04 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR       0x00210b08 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR       0x00210b0c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR        0x00210b10 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR      0x00210b14 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR 0x00210b18 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL 0x00210b1c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH          0x00210b20 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG       0x00210b24 /* Context 12 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB       0x00210b28 /* Context 12 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD       0x00210b2c /* Context 12 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF       0x00210b30 /* Context 12 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH       0x00210b34 /* Context 12 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1       0x00210b38 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2       0x00210b3c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3       0x00210b40 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES  0x00210b44 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL      0x00210b48 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL  0x00210b4c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL     0x00210b50 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL   0x00210b54 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL 0x00210b58 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL      0x00210b5c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL  0x00210b60 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL     0x00210b64 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL   0x00210b68 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL 0x00210b6c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode 0x00210b70 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID      0x00210b74 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1             0x00210b78 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX12_REC_INIT_TS           0x00210b7c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL           0x00210b80 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG       0x00210b84 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4       0x00210b88 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX12_PIC_CTR               0x00210b8c /* Picture Counter register */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE          0x00210b90 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX12_REC_TIMER             0x00210b94 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX12_REC_STATE0            0x00210b98 /* Record State Register */
#define BCHP_XPT_RAVE_CX12_REC_STATE1            0x00210b9c /* Record State Register */
#define BCHP_XPT_RAVE_CX12_REC_STATE2            0x00210ba0 /* Record State Register */
#define BCHP_XPT_RAVE_CX12_REC_STATE2b           0x00210ba4 /* Record State Register */
#define BCHP_XPT_RAVE_CX12_REC_STATE3            0x00210ba8 /* Record State Register */
#define BCHP_XPT_RAVE_CX12_REC_COUNT             0x00210bac /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL      0x00210bb0 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1    0x00210bb4 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_0            0x00210bb8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_1            0x00210bbc /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_2            0x00210bc0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_3            0x00210bc4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR      0x00210bc8 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR       0x00210bcc /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR       0x00210bd0 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR        0x00210bd4 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR      0x00210bd8 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR 0x00210bdc /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL 0x00210be0 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH          0x00210be4 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS         0x00210be8 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR      0x00210bec /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR       0x00210bf0 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR       0x00210bf4 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR        0x00210bf8 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR      0x00210bfc /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR 0x00210c00 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL 0x00210c04 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH          0x00210c08 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG       0x00210c0c /* Context 13 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB       0x00210c10 /* Context 13 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD       0x00210c14 /* Context 13 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF       0x00210c18 /* Context 13 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH       0x00210c1c /* Context 13 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1       0x00210c20 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2       0x00210c24 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3       0x00210c28 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES  0x00210c2c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL      0x00210c30 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL  0x00210c34 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL     0x00210c38 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL   0x00210c3c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL 0x00210c40 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL      0x00210c44 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL  0x00210c48 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL     0x00210c4c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL   0x00210c50 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL 0x00210c54 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE 0x00210c58 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID      0x00210c5c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1             0x00210c60 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX13_REC_INIT_TS           0x00210c64 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL           0x00210c68 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG       0x00210c6c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4       0x00210c70 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX13_PIC_CTR               0x00210c74 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE          0x00210c78 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX13_REC_TIMER             0x00210c7c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX13_REC_STATE0            0x00210c80 /* Record State Register */
#define BCHP_XPT_RAVE_CX13_REC_STATE1            0x00210c84 /* Record State Register */
#define BCHP_XPT_RAVE_CX13_REC_STATE2            0x00210c88 /* Record State Register */
#define BCHP_XPT_RAVE_CX13_REC_STATE2b           0x00210c8c /* Record State Register */
#define BCHP_XPT_RAVE_CX13_REC_STATE3            0x00210c90 /* Record State Register */
#define BCHP_XPT_RAVE_CX13_REC_COUNT             0x00210c94 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL      0x00210c98 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1    0x00210c9c /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_0            0x00210ca0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_1            0x00210ca4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_2            0x00210ca8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_3            0x00210cac /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR      0x00210cb0 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR       0x00210cb4 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR       0x00210cb8 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR        0x00210cbc /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR      0x00210cc0 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR 0x00210cc4 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL 0x00210cc8 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH          0x00210ccc /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS         0x00210cd0 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR      0x00210cd4 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR       0x00210cd8 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR       0x00210cdc /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR        0x00210ce0 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR      0x00210ce4 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR 0x00210ce8 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL 0x00210cec /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH          0x00210cf0 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG       0x00210cf4 /* Context 14 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB       0x00210cf8 /* Context 14 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD       0x00210cfc /* Context 14 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF       0x00210d00 /* Context 14 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH       0x00210d04 /* Context 14 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1       0x00210d08 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2       0x00210d0c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3       0x00210d10 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES  0x00210d14 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL      0x00210d18 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL  0x00210d1c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL     0x00210d20 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL   0x00210d24 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL 0x00210d28 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL      0x00210d2c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL  0x00210d30 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL     0x00210d34 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL   0x00210d38 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL 0x00210d3c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode 0x00210d40 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID      0x00210d44 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1             0x00210d48 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX14_REC_INIT_TS           0x00210d4c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL           0x00210d50 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG       0x00210d54 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4       0x00210d58 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX14_PIC_CTR               0x00210d5c /* Picture Counter register */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE          0x00210d60 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX14_REC_TIMER             0x00210d64 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX14_REC_STATE0            0x00210d68 /* Record State Register */
#define BCHP_XPT_RAVE_CX14_REC_STATE1            0x00210d6c /* Record State Register */
#define BCHP_XPT_RAVE_CX14_REC_STATE2            0x00210d70 /* Record State Register */
#define BCHP_XPT_RAVE_CX14_REC_STATE2b           0x00210d74 /* Record State Register */
#define BCHP_XPT_RAVE_CX14_REC_STATE3            0x00210d78 /* Record State Register */
#define BCHP_XPT_RAVE_CX14_REC_COUNT             0x00210d7c /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL      0x00210d80 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1    0x00210d84 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_0            0x00210d88 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_1            0x00210d8c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_2            0x00210d90 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_3            0x00210d94 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR      0x00210d98 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR       0x00210d9c /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR       0x00210da0 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR        0x00210da4 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR      0x00210da8 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR 0x00210dac /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL 0x00210db0 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH          0x00210db4 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS         0x00210db8 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR      0x00210dbc /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR       0x00210dc0 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR       0x00210dc4 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR        0x00210dc8 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR      0x00210dcc /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR 0x00210dd0 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL 0x00210dd4 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH          0x00210dd8 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG       0x00210ddc /* Context 15 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB       0x00210de0 /* Context 15 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD       0x00210de4 /* Context 15 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF       0x00210de8 /* Context 15 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH       0x00210dec /* Context 15 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1       0x00210df0 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2       0x00210df4 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3       0x00210df8 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES  0x00210dfc /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL      0x00210e00 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL  0x00210e04 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL     0x00210e08 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL   0x00210e0c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL 0x00210e10 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL      0x00210e14 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL  0x00210e18 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL     0x00210e1c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL   0x00210e20 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL 0x00210e24 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE 0x00210e28 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID      0x00210e2c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1             0x00210e30 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX15_REC_INIT_TS           0x00210e34 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL           0x00210e38 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG       0x00210e3c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4       0x00210e40 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX15_PIC_CTR               0x00210e44 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE          0x00210e48 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX15_REC_TIMER             0x00210e4c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX15_REC_STATE0            0x00210e50 /* Record State Register */
#define BCHP_XPT_RAVE_CX15_REC_STATE1            0x00210e54 /* Record State Register */
#define BCHP_XPT_RAVE_CX15_REC_STATE2            0x00210e58 /* Record State Register */
#define BCHP_XPT_RAVE_CX15_REC_STATE2b           0x00210e5c /* Record State Register */
#define BCHP_XPT_RAVE_CX15_REC_STATE3            0x00210e60 /* Record State Register */
#define BCHP_XPT_RAVE_CX15_REC_COUNT             0x00210e64 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL      0x00210e68 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1    0x00210e6c /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_0            0x00210e70 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_1            0x00210e74 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_2            0x00210e78 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_3            0x00210e7c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR      0x00210e80 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR       0x00210e84 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR       0x00210e88 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR        0x00210e8c /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR      0x00210e90 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR 0x00210e94 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL 0x00210e98 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH          0x00210e9c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS         0x00210ea0 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR      0x00210ea4 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR       0x00210ea8 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR       0x00210eac /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR        0x00210eb0 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR      0x00210eb4 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR 0x00210eb8 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL 0x00210ebc /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH          0x00210ec0 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG       0x00210ec4 /* Context 16 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB       0x00210ec8 /* Context 16 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD       0x00210ecc /* Context 16 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF       0x00210ed0 /* Context 16 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH       0x00210ed4 /* Context 16 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1       0x00210ed8 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2       0x00210edc /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3       0x00210ee0 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES  0x00210ee4 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL      0x00210ee8 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL  0x00210eec /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL     0x00210ef0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL   0x00210ef4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL 0x00210ef8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL      0x00210efc /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL  0x00210f00 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL     0x00210f04 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL   0x00210f08 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL 0x00210f0c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE 0x00210f10 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID      0x00210f14 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1             0x00210f18 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX16_REC_INIT_TS           0x00210f1c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL           0x00210f20 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG       0x00210f24 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4       0x00210f28 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX16_PIC_CTR               0x00210f2c /* Picture Counter register */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE          0x00210f30 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX16_REC_TIMER             0x00210f34 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX16_REC_STATE0            0x00210f38 /* Record State Register */
#define BCHP_XPT_RAVE_CX16_REC_STATE1            0x00210f3c /* Record State Register */
#define BCHP_XPT_RAVE_CX16_REC_STATE2            0x00210f40 /* Record State Register */
#define BCHP_XPT_RAVE_CX16_REC_STATE2b           0x00210f44 /* Record State Register */
#define BCHP_XPT_RAVE_CX16_REC_STATE3            0x00210f48 /* Record State Register */
#define BCHP_XPT_RAVE_CX16_REC_COUNT             0x00210f4c /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL      0x00210f50 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1    0x00210f54 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_0            0x00210f58 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_1            0x00210f5c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_2            0x00210f60 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_3            0x00210f64 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR      0x00210f68 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR       0x00210f6c /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR       0x00210f70 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR        0x00210f74 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR      0x00210f78 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR 0x00210f7c /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL 0x00210f80 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH          0x00210f84 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS         0x00210f88 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR      0x00210f8c /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR       0x00210f90 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR       0x00210f94 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR        0x00210f98 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR      0x00210f9c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR 0x00210fa0 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL 0x00210fa4 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH          0x00210fa8 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG       0x00210fac /* Context 17 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB       0x00210fb0 /* Context 17 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD       0x00210fb4 /* Context 17 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF       0x00210fb8 /* Context 17 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH       0x00210fbc /* Context 17 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1       0x00210fc0 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2       0x00210fc4 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3       0x00210fc8 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES  0x00210fcc /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL      0x00210fd0 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL  0x00210fd4 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL     0x00210fd8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL   0x00210fdc /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL 0x00210fe0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL      0x00210fe4 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL  0x00210fe8 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL     0x00210fec /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL   0x00210ff0 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL 0x00210ff4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE 0x00210ff8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID      0x00210ffc /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1             0x00211000 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX17_REC_INIT_TS           0x00211004 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL           0x00211008 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG       0x0021100c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4       0x00211010 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX17_PIC_CTR               0x00211014 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE          0x00211018 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX17_REC_TIMER             0x0021101c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX17_REC_STATE0            0x00211020 /* Record State Register */
#define BCHP_XPT_RAVE_CX17_REC_STATE1            0x00211024 /* Record State Register */
#define BCHP_XPT_RAVE_CX17_REC_STATE2            0x00211028 /* Record State Register */
#define BCHP_XPT_RAVE_CX17_REC_STATE2b           0x0021102c /* Record State Register */
#define BCHP_XPT_RAVE_CX17_REC_STATE3            0x00211030 /* Record State Register */
#define BCHP_XPT_RAVE_CX17_REC_COUNT             0x00211034 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL      0x00211038 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1    0x0021103c /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_0            0x00211040 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_1            0x00211044 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_2            0x00211048 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_3            0x0021104c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR      0x00211050 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR       0x00211054 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR       0x00211058 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR        0x0021105c /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR      0x00211060 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR 0x00211064 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL 0x00211068 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH          0x0021106c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS         0x00211070 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR      0x00211074 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR       0x00211078 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR       0x0021107c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR        0x00211080 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR      0x00211084 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR 0x00211088 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL 0x0021108c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH          0x00211090 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG       0x00211094 /* Context 18 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB       0x00211098 /* Context 18 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD       0x0021109c /* Context 18 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF       0x002110a0 /* Context 18 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH       0x002110a4 /* Context 18 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1       0x002110a8 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2       0x002110ac /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3       0x002110b0 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES  0x002110b4 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL      0x002110b8 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL  0x002110bc /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL     0x002110c0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL   0x002110c4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL 0x002110c8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL      0x002110cc /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL  0x002110d0 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL     0x002110d4 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL   0x002110d8 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL 0x002110dc /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE 0x002110e0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID      0x002110e4 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1             0x002110e8 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX18_REC_INIT_TS           0x002110ec /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL           0x002110f0 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG       0x002110f4 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4       0x002110f8 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX18_PIC_CTR               0x002110fc /* Picture Counter register */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE          0x00211100 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX18_REC_TIMER             0x00211104 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX18_REC_STATE0            0x00211108 /* Record State Register */
#define BCHP_XPT_RAVE_CX18_REC_STATE1            0x0021110c /* Record State Register */
#define BCHP_XPT_RAVE_CX18_REC_STATE2            0x00211110 /* Record State Register */
#define BCHP_XPT_RAVE_CX18_REC_STATE2b           0x00211114 /* Record State Register */
#define BCHP_XPT_RAVE_CX18_REC_STATE3            0x00211118 /* Record State Register */
#define BCHP_XPT_RAVE_CX18_REC_COUNT             0x0021111c /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL      0x00211120 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1    0x00211124 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_0            0x00211128 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_1            0x0021112c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_2            0x00211130 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_3            0x00211134 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR      0x00211138 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR       0x0021113c /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR       0x00211140 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR        0x00211144 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR      0x00211148 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR 0x0021114c /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL 0x00211150 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH          0x00211154 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS         0x00211158 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR      0x0021115c /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR       0x00211160 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR       0x00211164 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR        0x00211168 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR      0x0021116c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR 0x00211170 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL 0x00211174 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH          0x00211178 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG       0x0021117c /* Context 19 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB       0x00211180 /* Context 19 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD       0x00211184 /* Context 19 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF       0x00211188 /* Context 19 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH       0x0021118c /* Context 19 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1       0x00211190 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2       0x00211194 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3       0x00211198 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES  0x0021119c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL      0x002111a0 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL  0x002111a4 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL     0x002111a8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL   0x002111ac /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL 0x002111b0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL      0x002111b4 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL  0x002111b8 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL     0x002111bc /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL   0x002111c0 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL 0x002111c4 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE 0x002111c8 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID      0x002111cc /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1             0x002111d0 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX19_REC_INIT_TS           0x002111d4 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL           0x002111d8 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG       0x002111dc /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4       0x002111e0 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX19_PIC_CTR               0x002111e4 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE          0x002111e8 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX19_REC_TIMER             0x002111ec /* Record Timer Register */
#define BCHP_XPT_RAVE_CX19_REC_STATE0            0x002111f0 /* Record State Register */
#define BCHP_XPT_RAVE_CX19_REC_STATE1            0x002111f4 /* Record State Register */
#define BCHP_XPT_RAVE_CX19_REC_STATE2            0x002111f8 /* Record State Register */
#define BCHP_XPT_RAVE_CX19_REC_STATE2b           0x002111fc /* Record State Register */
#define BCHP_XPT_RAVE_CX19_REC_STATE3            0x00211200 /* Record State Register */
#define BCHP_XPT_RAVE_CX19_REC_COUNT             0x00211204 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL      0x00211208 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1    0x0021120c /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_0            0x00211210 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_1            0x00211214 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_2            0x00211218 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_3            0x0021121c /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR      0x00211220 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR       0x00211224 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR       0x00211228 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR        0x0021122c /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR      0x00211230 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR 0x00211234 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL 0x00211238 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH          0x0021123c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS         0x00211240 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR      0x00211244 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR       0x00211248 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR       0x0021124c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR        0x00211250 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR      0x00211254 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR 0x00211258 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL 0x0021125c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH          0x00211260 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG       0x00211264 /* Context 20 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB       0x00211268 /* Context 20 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD       0x0021126c /* Context 20 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF       0x00211270 /* Context 20 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH       0x00211274 /* Context 20 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1       0x00211278 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2       0x0021127c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3       0x00211280 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES  0x00211284 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL      0x00211288 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL  0x0021128c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL     0x00211290 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL   0x00211294 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL 0x00211298 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL      0x0021129c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL  0x002112a0 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL     0x002112a4 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL   0x002112a8 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL 0x002112ac /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode 0x002112b0 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID      0x002112b4 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1             0x002112b8 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX20_REC_INIT_TS           0x002112bc /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL           0x002112c0 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG       0x002112c4 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4       0x002112c8 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX20_PIC_CTR               0x002112cc /* Picture Counter register */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE          0x002112d0 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX20_REC_TIMER             0x002112d4 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX20_REC_STATE0            0x002112d8 /* Record State Register */
#define BCHP_XPT_RAVE_CX20_REC_STATE1            0x002112dc /* Record State Register */
#define BCHP_XPT_RAVE_CX20_REC_STATE2            0x002112e0 /* Record State Register */
#define BCHP_XPT_RAVE_CX20_REC_STATE2b           0x002112e4 /* Record State Register */
#define BCHP_XPT_RAVE_CX20_REC_STATE3            0x002112e8 /* Record State Register */
#define BCHP_XPT_RAVE_CX20_REC_COUNT             0x002112ec /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL      0x002112f0 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1    0x002112f4 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_0            0x002112f8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_1            0x002112fc /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_2            0x00211300 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_3            0x00211304 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR      0x00211308 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR       0x0021130c /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR       0x00211310 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR        0x00211314 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR      0x00211318 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR 0x0021131c /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL 0x00211320 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH          0x00211324 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS         0x00211328 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR      0x0021132c /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR       0x00211330 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR       0x00211334 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR        0x00211338 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR      0x0021133c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR 0x00211340 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL 0x00211344 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH          0x00211348 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG       0x0021134c /* Context 21 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB       0x00211350 /* Context 21 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD       0x00211354 /* Context 21 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF       0x00211358 /* Context 21 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH       0x0021135c /* Context 21 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1       0x00211360 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2       0x00211364 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3       0x00211368 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES  0x0021136c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL      0x00211370 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL  0x00211374 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL     0x00211378 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL   0x0021137c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL 0x00211380 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL      0x00211384 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL  0x00211388 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL     0x0021138c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL   0x00211390 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL 0x00211394 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE 0x00211398 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID      0x0021139c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1             0x002113a0 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX21_REC_INIT_TS           0x002113a4 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL           0x002113a8 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG       0x002113ac /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4       0x002113b0 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX21_PIC_CTR               0x002113b4 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE          0x002113b8 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX21_REC_TIMER             0x002113bc /* Record Timer Register */
#define BCHP_XPT_RAVE_CX21_REC_STATE0            0x002113c0 /* Record State Register */
#define BCHP_XPT_RAVE_CX21_REC_STATE1            0x002113c4 /* Record State Register */
#define BCHP_XPT_RAVE_CX21_REC_STATE2            0x002113c8 /* Record State Register */
#define BCHP_XPT_RAVE_CX21_REC_STATE2b           0x002113cc /* Record State Register */
#define BCHP_XPT_RAVE_CX21_REC_STATE3            0x002113d0 /* Record State Register */
#define BCHP_XPT_RAVE_CX21_REC_COUNT             0x002113d4 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL      0x002113d8 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1    0x002113dc /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_0            0x002113e0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_1            0x002113e4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_2            0x002113e8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_3            0x002113ec /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR      0x002113f0 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR       0x002113f4 /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR       0x002113f8 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR        0x002113fc /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR      0x00211400 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR 0x00211404 /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL 0x00211408 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH          0x0021140c /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS         0x00211410 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR      0x00211414 /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR       0x00211418 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR       0x0021141c /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR        0x00211420 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR      0x00211424 /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR 0x00211428 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL 0x0021142c /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH          0x00211430 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG       0x00211434 /* Context 22 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB       0x00211438 /* Context 22 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD       0x0021143c /* Context 22 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF       0x00211440 /* Context 22 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH       0x00211444 /* Context 22 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1       0x00211448 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2       0x0021144c /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3       0x00211450 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES  0x00211454 /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL      0x00211458 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL  0x0021145c /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL     0x00211460 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL   0x00211464 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL 0x00211468 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL      0x0021146c /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL  0x00211470 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL     0x00211474 /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL   0x00211478 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL 0x0021147c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode 0x00211480 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID      0x00211484 /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1             0x00211488 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX22_REC_INIT_TS           0x0021148c /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL           0x00211490 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG       0x00211494 /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4       0x00211498 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX22_PIC_CTR               0x0021149c /* Picture Counter register */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE          0x002114a0 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX22_REC_TIMER             0x002114a4 /* Record Timer Register */
#define BCHP_XPT_RAVE_CX22_REC_STATE0            0x002114a8 /* Record State Register */
#define BCHP_XPT_RAVE_CX22_REC_STATE1            0x002114ac /* Record State Register */
#define BCHP_XPT_RAVE_CX22_REC_STATE2            0x002114b0 /* Record State Register */
#define BCHP_XPT_RAVE_CX22_REC_STATE2b           0x002114b4 /* Record State Register */
#define BCHP_XPT_RAVE_CX22_REC_STATE3            0x002114b8 /* Record State Register */
#define BCHP_XPT_RAVE_CX22_REC_COUNT             0x002114bc /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL      0x002114c0 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1    0x002114c4 /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_0            0x002114c8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_1            0x002114cc /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_2            0x002114d0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_3            0x002114d4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR      0x002114d8 /* Context CDB Write Pointer */
#define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR       0x002114dc /* Context CDB Read Pointer */
#define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR       0x002114e0 /* Context CDB Base Pointer */
#define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR        0x002114e4 /* Context CDB End Pointer */
#define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR      0x002114e8 /* Context CDB Valid Pointer */
#define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR 0x002114ec /* Context CDB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL 0x002114f0 /* Context CDB Watermark Level */
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH          0x002114f4 /* Context CDB Depth */
#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS         0x002114f8 /* Context Thresholds */
#define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR      0x002114fc /* Context ITB Write Pointer */
#define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR       0x00211500 /* Context ITB Read Pointer */
#define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR       0x00211504 /* Context ITB Base Pointer */
#define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR        0x00211508 /* Context ITB End Pointer */
#define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR      0x0021150c /* Context ITB Valid Pointer */
#define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR 0x00211510 /* Context ITB Wraparound Pointer */
#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL 0x00211514 /* Context ITB Watermark Level */
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH          0x00211518 /* Context ITB Depth */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG       0x0021151c /* Context 23 Miscellaneous Config */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB       0x00211520 /* Context 23 SCD map PIDS A and B */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD       0x00211524 /* Context 23 SCD map PIDS C and D */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF       0x00211528 /* Context 23 SCD map PIDS E and F */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH       0x0021152c /* Context 23 SCD map PIDS G and H */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1       0x00211530 /* Context Miscellaneous Config 1 Register */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2       0x00211534 /* Context Miscellaneous Config 2 Register */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3       0x00211538 /* Context Miscellaneous Config 3 Register */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES  0x0021153c /* Context Interrupt Enables */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL      0x00211540 /* Context Comparator 1 Control Register */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL  0x00211544 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL     0x00211548 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL   0x0021154c /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL 0x00211550 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL      0x00211554 /* Context Comparator 2 Control Register */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL  0x00211558 /* Context Comparator 2 32-bit compare value */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL     0x0021155c /* Context Comparator 2 32-bit mask value */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL   0x00211560 /* Context Comparator 1 32-bit compare value */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL 0x00211564 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE 0x00211568 /* Context Comparator 1 32-bit mask value */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID      0x0021156c /* Context PID and Stream ID Filter Value */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1             0x00211570 /* Record Control Register 1 */
#define BCHP_XPT_RAVE_CX23_REC_INIT_TS           0x00211574 /* Record Initial Timestamp Value Register */
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL           0x00211578 /* Record Timestamp Control Register */
#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG       0x0021157c /* Record Time Configuration Register */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4       0x00211580 /* Context Miscellaneous Config 4 Register */
#define BCHP_XPT_RAVE_CX23_PIC_CTR               0x00211584 /* Picture Counter register */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE          0x00211588 /* Picture Counter Mode Register */
#define BCHP_XPT_RAVE_CX23_REC_TIMER             0x0021158c /* Record Timer Register */
#define BCHP_XPT_RAVE_CX23_REC_STATE0            0x00211590 /* Record State Register */
#define BCHP_XPT_RAVE_CX23_REC_STATE1            0x00211594 /* Record State Register */
#define BCHP_XPT_RAVE_CX23_REC_STATE2            0x00211598 /* Record State Register */
#define BCHP_XPT_RAVE_CX23_REC_STATE2b           0x0021159c /* Record State Register */
#define BCHP_XPT_RAVE_CX23_REC_STATE3            0x002115a0 /* Record State Register */
#define BCHP_XPT_RAVE_CX23_REC_COUNT             0x002115a4 /* Record Packet Count Register */
#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL      0x002115a8 /* Picture Counter Increment/Decrement/Reset Control Register */
#define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1    0x002115ac /* Reserved Record State Register */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_0            0x002115b0 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_1            0x002115b4 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_2            0x002115b8 /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_3            0x002115bc /* Reserved Rave Register for future use */
#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG       0x002115c0 /* SCD 0 Misc Config Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0       0x002115c4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1       0x002115c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2       0x002115cc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3       0x002115d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4       0x002115d4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5       0x002115d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6       0x002115dc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7       0x002115e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8       0x002115e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9       0x002115e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10      0x002115ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11      0x002115f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0   0x002115f4 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0        0x002115f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1        0x002115fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2        0x00211600 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3        0x00211604 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT      0x00211608 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0    0x0021160c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1    0x00211610 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE0            0x00211614 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE1            0x00211618 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE2            0x0021161c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE3            0x00211620 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE4            0x00211624 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE5            0x00211628 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0       0x0021162c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1       0x00211630 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2       0x00211634 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3       0x00211638 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG       0x0021163c /* SCD 1 Misc Config Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0       0x00211640 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1       0x00211644 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2       0x00211648 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3       0x0021164c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4       0x00211650 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5       0x00211654 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6       0x00211658 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7       0x0021165c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8       0x00211660 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9       0x00211664 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10      0x00211668 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11      0x0021166c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0   0x00211670 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0        0x00211674 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1        0x00211678 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2        0x0021167c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3        0x00211680 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT      0x00211684 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0    0x00211688 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1    0x0021168c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE0            0x00211690 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE1            0x00211694 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE2            0x00211698 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE3            0x0021169c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE4            0x002116a0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE5            0x002116a4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0       0x002116a8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1       0x002116ac /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2       0x002116b0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3       0x002116b4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG       0x002116b8 /* SCD 2 Misc Config Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0       0x002116bc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1       0x002116c0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2       0x002116c4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3       0x002116c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4       0x002116cc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5       0x002116d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6       0x002116d4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7       0x002116d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8       0x002116dc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9       0x002116e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10      0x002116e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11      0x002116e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0   0x002116ec /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0        0x002116f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1        0x002116f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2        0x002116f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3        0x002116fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT      0x00211700 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0    0x00211704 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1    0x00211708 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE0            0x0021170c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE1            0x00211710 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE2            0x00211714 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE3            0x00211718 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE4            0x0021171c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE5            0x00211720 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0       0x00211724 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1       0x00211728 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2       0x0021172c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3       0x00211730 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG       0x00211734 /* SCD 3 Misc Config Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0       0x00211738 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1       0x0021173c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2       0x00211740 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3       0x00211744 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4       0x00211748 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5       0x0021174c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6       0x00211750 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7       0x00211754 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8       0x00211758 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9       0x0021175c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10      0x00211760 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11      0x00211764 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0   0x00211768 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0        0x0021176c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1        0x00211770 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2        0x00211774 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3        0x00211778 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT      0x0021177c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0    0x00211780 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1    0x00211784 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE0            0x00211788 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE1            0x0021178c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE2            0x00211790 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE3            0x00211794 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE4            0x00211798 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE5            0x0021179c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0       0x002117a0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1       0x002117a4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2       0x002117a8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3       0x002117ac /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG       0x002117b0 /* SCD 4 Misc Config Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0       0x002117b4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1       0x002117b8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2       0x002117bc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3       0x002117c0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4       0x002117c4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5       0x002117c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6       0x002117cc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7       0x002117d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8       0x002117d4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9       0x002117d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10      0x002117dc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11      0x002117e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0   0x002117e4 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0        0x002117e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1        0x002117ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2        0x002117f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3        0x002117f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT      0x002117f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0    0x002117fc /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1    0x00211800 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE0            0x00211804 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE1            0x00211808 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE2            0x0021180c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE3            0x00211810 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE4            0x00211814 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE5            0x00211818 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0       0x0021181c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1       0x00211820 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2       0x00211824 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3       0x00211828 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG       0x0021182c /* SCD 5 Misc Config Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0       0x00211830 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1       0x00211834 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2       0x00211838 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3       0x0021183c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4       0x00211840 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5       0x00211844 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6       0x00211848 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7       0x0021184c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8       0x00211850 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9       0x00211854 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10      0x00211858 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11      0x0021185c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0   0x00211860 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0        0x00211864 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1        0x00211868 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2        0x0021186c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3        0x00211870 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT      0x00211874 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0    0x00211878 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1    0x0021187c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE0            0x00211880 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE1            0x00211884 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE2            0x00211888 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE3            0x0021188c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE4            0x00211890 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE5            0x00211894 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0       0x00211898 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1       0x0021189c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2       0x002118a0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3       0x002118a4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG       0x002118a8 /* SCD 6 Misc Config Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0       0x002118ac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1       0x002118b0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2       0x002118b4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3       0x002118b8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4       0x002118bc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5       0x002118c0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6       0x002118c4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7       0x002118c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8       0x002118cc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9       0x002118d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10      0x002118d4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11      0x002118d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0   0x002118dc /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0        0x002118e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1        0x002118e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2        0x002118e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3        0x002118ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT      0x002118f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0    0x002118f4 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1    0x002118f8 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE0            0x002118fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE1            0x00211900 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE2            0x00211904 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE3            0x00211908 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE4            0x0021190c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE5            0x00211910 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0       0x00211914 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1       0x00211918 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2       0x0021191c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3       0x00211920 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG       0x00211924 /* SCD 7 Misc Config Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0       0x00211928 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1       0x0021192c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2       0x00211930 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3       0x00211934 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4       0x00211938 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5       0x0021193c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6       0x00211940 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7       0x00211944 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8       0x00211948 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9       0x0021194c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10      0x00211950 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11      0x00211954 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0   0x00211958 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0        0x0021195c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1        0x00211960 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2        0x00211964 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3        0x00211968 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT      0x0021196c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0    0x00211970 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1    0x00211974 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE0            0x00211978 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE1            0x0021197c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE2            0x00211980 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE3            0x00211984 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE4            0x00211988 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE5            0x0021198c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0       0x00211990 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1       0x00211994 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2       0x00211998 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3       0x0021199c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG       0x002119a0 /* SCD 8 Misc Config Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0       0x002119a4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1       0x002119a8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2       0x002119ac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3       0x002119b0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4       0x002119b4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5       0x002119b8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6       0x002119bc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7       0x002119c0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8       0x002119c4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9       0x002119c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10      0x002119cc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11      0x002119d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0   0x002119d4 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0        0x002119d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1        0x002119dc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2        0x002119e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3        0x002119e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT      0x002119e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0    0x002119ec /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1    0x002119f0 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE0            0x002119f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE1            0x002119f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE2            0x002119fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE3            0x00211a00 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE4            0x00211a04 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE5            0x00211a08 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0       0x00211a0c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1       0x00211a10 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2       0x00211a14 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3       0x00211a18 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG       0x00211a1c /* SCD 9 Misc Config Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0       0x00211a20 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1       0x00211a24 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2       0x00211a28 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3       0x00211a2c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4       0x00211a30 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5       0x00211a34 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6       0x00211a38 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7       0x00211a3c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8       0x00211a40 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9       0x00211a44 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10      0x00211a48 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11      0x00211a4c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0   0x00211a50 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0        0x00211a54 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1        0x00211a58 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2        0x00211a5c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3        0x00211a60 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT      0x00211a64 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0    0x00211a68 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1    0x00211a6c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE0            0x00211a70 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE1            0x00211a74 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE2            0x00211a78 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE3            0x00211a7c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE4            0x00211a80 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE5            0x00211a84 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0       0x00211a88 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1       0x00211a8c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2       0x00211a90 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3       0x00211a94 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG      0x00211a98 /* SCD 10 Misc Config Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0      0x00211a9c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1      0x00211aa0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2      0x00211aa4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3      0x00211aa8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4      0x00211aac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5      0x00211ab0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6      0x00211ab4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7      0x00211ab8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8      0x00211abc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9      0x00211ac0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10     0x00211ac4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11     0x00211ac8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0  0x00211acc /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0       0x00211ad0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1       0x00211ad4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2       0x00211ad8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3       0x00211adc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT     0x00211ae0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0   0x00211ae4 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1   0x00211ae8 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE0           0x00211aec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE1           0x00211af0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE2           0x00211af4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE3           0x00211af8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE4           0x00211afc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE5           0x00211b00 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0      0x00211b04 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1      0x00211b08 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2      0x00211b0c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3      0x00211b10 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG      0x00211b14 /* SCD 11 Misc Config Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0      0x00211b18 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1      0x00211b1c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2      0x00211b20 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3      0x00211b24 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4      0x00211b28 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5      0x00211b2c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6      0x00211b30 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7      0x00211b34 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8      0x00211b38 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9      0x00211b3c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10     0x00211b40 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11     0x00211b44 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0  0x00211b48 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0       0x00211b4c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1       0x00211b50 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2       0x00211b54 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3       0x00211b58 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT     0x00211b5c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0   0x00211b60 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1   0x00211b64 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE0           0x00211b68 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE1           0x00211b6c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE2           0x00211b70 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE3           0x00211b74 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE4           0x00211b78 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE5           0x00211b7c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0      0x00211b80 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1      0x00211b84 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2      0x00211b88 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3      0x00211b8c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG      0x00211b90 /* SCD 12 Misc Config Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0      0x00211b94 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1      0x00211b98 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2      0x00211b9c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3      0x00211ba0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4      0x00211ba4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5      0x00211ba8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6      0x00211bac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7      0x00211bb0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8      0x00211bb4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9      0x00211bb8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10     0x00211bbc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11     0x00211bc0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0  0x00211bc4 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0       0x00211bc8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1       0x00211bcc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2       0x00211bd0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3       0x00211bd4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT     0x00211bd8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0   0x00211bdc /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1   0x00211be0 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE0           0x00211be4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE1           0x00211be8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE2           0x00211bec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE3           0x00211bf0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE4           0x00211bf4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE5           0x00211bf8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0      0x00211bfc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1      0x00211c00 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2      0x00211c04 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3      0x00211c08 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG      0x00211c0c /* SCD 13 Misc Config Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0      0x00211c10 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1      0x00211c14 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2      0x00211c18 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3      0x00211c1c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4      0x00211c20 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5      0x00211c24 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6      0x00211c28 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7      0x00211c2c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8      0x00211c30 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9      0x00211c34 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10     0x00211c38 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11     0x00211c3c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0  0x00211c40 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0       0x00211c44 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1       0x00211c48 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2       0x00211c4c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3       0x00211c50 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT     0x00211c54 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0   0x00211c58 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1   0x00211c5c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE0           0x00211c60 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE1           0x00211c64 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE2           0x00211c68 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE3           0x00211c6c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE4           0x00211c70 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE5           0x00211c74 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0      0x00211c78 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1      0x00211c7c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2      0x00211c80 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3      0x00211c84 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG      0x00211c88 /* SCD 14 Misc Config Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0      0x00211c8c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1      0x00211c90 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2      0x00211c94 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3      0x00211c98 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4      0x00211c9c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5      0x00211ca0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6      0x00211ca4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7      0x00211ca8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8      0x00211cac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9      0x00211cb0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10     0x00211cb4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11     0x00211cb8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0  0x00211cbc /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0       0x00211cc0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1       0x00211cc4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2       0x00211cc8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3       0x00211ccc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT     0x00211cd0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0   0x00211cd4 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1   0x00211cd8 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE0           0x00211cdc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE1           0x00211ce0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE2           0x00211ce4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE3           0x00211ce8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE4           0x00211cec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE5           0x00211cf0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0      0x00211cf4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1      0x00211cf8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2      0x00211cfc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3      0x00211d00 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG      0x00211d04 /* SCD 15 Misc Config Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0      0x00211d08 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1      0x00211d0c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2      0x00211d10 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3      0x00211d14 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4      0x00211d18 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5      0x00211d1c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6      0x00211d20 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7      0x00211d24 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8      0x00211d28 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9      0x00211d2c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10     0x00211d30 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11     0x00211d34 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0  0x00211d38 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0       0x00211d3c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1       0x00211d40 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2       0x00211d44 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3       0x00211d48 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT     0x00211d4c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0   0x00211d50 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1   0x00211d54 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE0           0x00211d58 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE1           0x00211d5c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE2           0x00211d60 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE3           0x00211d64 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE4           0x00211d68 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE5           0x00211d6c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0      0x00211d70 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1      0x00211d74 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2      0x00211d78 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3      0x00211d7c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG      0x00211d80 /* SCD 16 Misc Config Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0      0x00211d84 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1      0x00211d88 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2      0x00211d8c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3      0x00211d90 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4      0x00211d94 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5      0x00211d98 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6      0x00211d9c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7      0x00211da0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8      0x00211da4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9      0x00211da8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10     0x00211dac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11     0x00211db0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0  0x00211db4 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0       0x00211db8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1       0x00211dbc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2       0x00211dc0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3       0x00211dc4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT     0x00211dc8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0   0x00211dcc /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1   0x00211dd0 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE0           0x00211dd4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE1           0x00211dd8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE2           0x00211ddc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE3           0x00211de0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE4           0x00211de4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE5           0x00211de8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0      0x00211dec /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1      0x00211df0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2      0x00211df4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3      0x00211df8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG      0x00211dfc /* SCD 17 Misc Config Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0      0x00211e00 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1      0x00211e04 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2      0x00211e08 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3      0x00211e0c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4      0x00211e10 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5      0x00211e14 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6      0x00211e18 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7      0x00211e1c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8      0x00211e20 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9      0x00211e24 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10     0x00211e28 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11     0x00211e2c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0  0x00211e30 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0       0x00211e34 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1       0x00211e38 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2       0x00211e3c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3       0x00211e40 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT     0x00211e44 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0   0x00211e48 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1   0x00211e4c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE0           0x00211e50 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE1           0x00211e54 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE2           0x00211e58 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE3           0x00211e5c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE4           0x00211e60 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE5           0x00211e64 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0      0x00211e68 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1      0x00211e6c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2      0x00211e70 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3      0x00211e74 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG      0x00211e78 /* SCD 18 Misc Config Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0      0x00211e7c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1      0x00211e80 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2      0x00211e84 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3      0x00211e88 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4      0x00211e8c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5      0x00211e90 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6      0x00211e94 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7      0x00211e98 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8      0x00211e9c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9      0x00211ea0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10     0x00211ea4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11     0x00211ea8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0  0x00211eac /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0       0x00211eb0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1       0x00211eb4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2       0x00211eb8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3       0x00211ebc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT     0x00211ec0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0   0x00211ec4 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1   0x00211ec8 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE0           0x00211ecc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE1           0x00211ed0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE2           0x00211ed4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE3           0x00211ed8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE4           0x00211edc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE5           0x00211ee0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0      0x00211ee4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1      0x00211ee8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2      0x00211eec /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3      0x00211ef0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG      0x00211ef4 /* SCD 19 Misc Config Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0      0x00211ef8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1      0x00211efc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2      0x00211f00 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3      0x00211f04 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4      0x00211f08 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5      0x00211f0c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6      0x00211f10 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7      0x00211f14 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8      0x00211f18 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9      0x00211f1c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10     0x00211f20 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11     0x00211f24 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0  0x00211f28 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0       0x00211f2c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1       0x00211f30 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2       0x00211f34 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3       0x00211f38 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT     0x00211f3c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0   0x00211f40 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1   0x00211f44 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE0           0x00211f48 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE1           0x00211f4c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE2           0x00211f50 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE3           0x00211f54 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE4           0x00211f58 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE5           0x00211f5c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0      0x00211f60 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1      0x00211f64 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2      0x00211f68 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3      0x00211f6c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG      0x00211f70 /* SCD 20 Misc Config Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0      0x00211f74 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1      0x00211f78 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2      0x00211f7c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3      0x00211f80 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4      0x00211f84 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5      0x00211f88 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6      0x00211f8c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7      0x00211f90 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8      0x00211f94 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9      0x00211f98 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10     0x00211f9c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11     0x00211fa0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0  0x00211fa4 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0       0x00211fa8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1       0x00211fac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2       0x00211fb0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3       0x00211fb4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT     0x00211fb8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0   0x00211fbc /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1   0x00211fc0 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE0           0x00211fc4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE1           0x00211fc8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE2           0x00211fcc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE3           0x00211fd0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE4           0x00211fd4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE5           0x00211fd8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0      0x00211fdc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1      0x00211fe0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2      0x00211fe4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3      0x00211fe8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG      0x00211fec /* SCD 21 Misc Config Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0      0x00211ff0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1      0x00211ff4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2      0x00211ff8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3      0x00211ffc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4      0x00212000 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5      0x00212004 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6      0x00212008 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7      0x0021200c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8      0x00212010 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9      0x00212014 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10     0x00212018 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11     0x0021201c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0  0x00212020 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0       0x00212024 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1       0x00212028 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2       0x0021202c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3       0x00212030 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT     0x00212034 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0   0x00212038 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1   0x0021203c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE0           0x00212040 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE1           0x00212044 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE2           0x00212048 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE3           0x0021204c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE4           0x00212050 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE5           0x00212054 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0      0x00212058 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1      0x0021205c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2      0x00212060 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3      0x00212064 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG      0x00212068 /* SCD 22 Misc Config Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0      0x0021206c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1      0x00212070 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2      0x00212074 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3      0x00212078 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4      0x0021207c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5      0x00212080 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6      0x00212084 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7      0x00212088 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8      0x0021208c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9      0x00212090 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10     0x00212094 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11     0x00212098 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0  0x0021209c /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0       0x002120a0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1       0x002120a4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2       0x002120a8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3       0x002120ac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT     0x002120b0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0   0x002120b4 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1   0x002120b8 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE0           0x002120bc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE1           0x002120c0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE2           0x002120c4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE3           0x002120c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE4           0x002120cc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE5           0x002120d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0      0x002120d4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1      0x002120d8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2      0x002120dc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3      0x002120e0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG      0x002120e4 /* SCD 23 Misc Config Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0      0x002120e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1      0x002120ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2      0x002120f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3      0x002120f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4      0x002120f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5      0x002120fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6      0x00212100 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7      0x00212104 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8      0x00212108 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9      0x0021210c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10     0x00212110 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11     0x00212114 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0  0x00212118 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0       0x0021211c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1       0x00212120 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2       0x00212124 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3       0x00212128 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT     0x0021212c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0   0x00212130 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1   0x00212134 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE0           0x00212138 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE1           0x0021213c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE2           0x00212140 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE3           0x00212144 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE4           0x00212148 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE5           0x0021214c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0      0x00212150 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1      0x00212154 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2      0x00212158 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3      0x0021215c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG      0x00212160 /* SCD 24 Misc Config Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0      0x00212164 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1      0x00212168 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2      0x0021216c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3      0x00212170 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4      0x00212174 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5      0x00212178 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6      0x0021217c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7      0x00212180 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8      0x00212184 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9      0x00212188 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10     0x0021218c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11     0x00212190 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0  0x00212194 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0       0x00212198 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1       0x0021219c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2       0x002121a0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3       0x002121a4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT     0x002121a8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0   0x002121ac /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1   0x002121b0 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE0           0x002121b4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE1           0x002121b8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE2           0x002121bc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE3           0x002121c0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE4           0x002121c4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE5           0x002121c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0      0x002121cc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1      0x002121d0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2      0x002121d4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3      0x002121d8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG      0x002121dc /* SCD 25 Misc Config Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0      0x002121e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1      0x002121e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2      0x002121e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3      0x002121ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4      0x002121f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5      0x002121f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6      0x002121f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7      0x002121fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8      0x00212200 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9      0x00212204 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10     0x00212208 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11     0x0021220c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0  0x00212210 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0       0x00212214 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1       0x00212218 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2       0x0021221c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3       0x00212220 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT     0x00212224 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0   0x00212228 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1   0x0021222c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE0           0x00212230 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE1           0x00212234 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE2           0x00212238 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE3           0x0021223c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE4           0x00212240 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE5           0x00212244 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0      0x00212248 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1      0x0021224c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2      0x00212250 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3      0x00212254 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG      0x00212258 /* SCD 26 Misc Config Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0      0x0021225c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1      0x00212260 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2      0x00212264 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3      0x00212268 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4      0x0021226c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5      0x00212270 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6      0x00212274 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7      0x00212278 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8      0x0021227c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9      0x00212280 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10     0x00212284 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11     0x00212288 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0  0x0021228c /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0       0x00212290 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1       0x00212294 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2       0x00212298 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3       0x0021229c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT     0x002122a0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0   0x002122a4 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1   0x002122a8 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE0           0x002122ac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE1           0x002122b0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE2           0x002122b4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE3           0x002122b8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE4           0x002122bc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE5           0x002122c0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0      0x002122c4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1      0x002122c8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2      0x002122cc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3      0x002122d0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG      0x002122d4 /* SCD 27 Misc Config Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0      0x002122d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1      0x002122dc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2      0x002122e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3      0x002122e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4      0x002122e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5      0x002122ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6      0x002122f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7      0x002122f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8      0x002122f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9      0x002122fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10     0x00212300 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11     0x00212304 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0  0x00212308 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0       0x0021230c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1       0x00212310 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2       0x00212314 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3       0x00212318 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT     0x0021231c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0   0x00212320 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1   0x00212324 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE0           0x00212328 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE1           0x0021232c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE2           0x00212330 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE3           0x00212334 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE4           0x00212338 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE5           0x0021233c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0      0x00212340 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1      0x00212344 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2      0x00212348 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3      0x0021234c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG      0x00212350 /* SCD 28 Misc Config Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0      0x00212354 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1      0x00212358 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2      0x0021235c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3      0x00212360 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4      0x00212364 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5      0x00212368 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6      0x0021236c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7      0x00212370 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8      0x00212374 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9      0x00212378 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10     0x0021237c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11     0x00212380 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0  0x00212384 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0       0x00212388 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1       0x0021238c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2       0x00212390 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3       0x00212394 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT     0x00212398 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0   0x0021239c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1   0x002123a0 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE0           0x002123a4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE1           0x002123a8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE2           0x002123ac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE3           0x002123b0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE4           0x002123b4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE5           0x002123b8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0      0x002123bc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1      0x002123c0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2      0x002123c4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3      0x002123c8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG      0x002123cc /* SCD 29 Misc Config Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0      0x002123d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1      0x002123d4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2      0x002123d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3      0x002123dc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4      0x002123e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5      0x002123e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6      0x002123e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7      0x002123ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8      0x002123f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9      0x002123f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10     0x002123f8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11     0x002123fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0  0x00212400 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0       0x00212404 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1       0x00212408 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2       0x0021240c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3       0x00212410 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT     0x00212414 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0   0x00212418 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1   0x0021241c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE0           0x00212420 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE1           0x00212424 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE2           0x00212428 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE3           0x0021242c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE4           0x00212430 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE5           0x00212434 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0      0x00212438 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1      0x0021243c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2      0x00212440 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3      0x00212444 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG      0x00212448 /* SCD 30 Misc Config Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0      0x0021244c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1      0x00212450 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2      0x00212454 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3      0x00212458 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4      0x0021245c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5      0x00212460 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6      0x00212464 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7      0x00212468 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8      0x0021246c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9      0x00212470 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10     0x00212474 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11     0x00212478 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0  0x0021247c /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0       0x00212480 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1       0x00212484 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2       0x00212488 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3       0x0021248c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT     0x00212490 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0   0x00212494 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1   0x00212498 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE0           0x0021249c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE1           0x002124a0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE2           0x002124a4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE3           0x002124a8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE4           0x002124ac /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE5           0x002124b0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0      0x002124b4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1      0x002124b8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2      0x002124bc /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3      0x002124c0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG      0x002124c4 /* SCD 31 Misc Config Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0      0x002124c8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1      0x002124cc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2      0x002124d0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3      0x002124d4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4      0x002124d8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5      0x002124dc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6      0x002124e0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7      0x002124e4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8      0x002124e8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9      0x002124ec /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10     0x002124f0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11     0x002124f4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0  0x002124f8 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0       0x002124fc /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1       0x00212500 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2       0x00212504 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3       0x00212508 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT     0x0021250c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0   0x00212510 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1   0x00212514 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE0           0x00212518 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE1           0x0021251c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE2           0x00212520 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE3           0x00212524 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE4           0x00212528 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE5           0x0021252c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0      0x00212530 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1      0x00212534 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2      0x00212538 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3      0x0021253c /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG      0x00212540 /* SCD 32 Misc Config Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0      0x00212544 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1      0x00212548 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2      0x0021254c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3      0x00212550 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4      0x00212554 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5      0x00212558 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6      0x0021255c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7      0x00212560 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8      0x00212564 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9      0x00212568 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10     0x0021256c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11     0x00212570 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0  0x00212574 /* Reserved Comparator State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0       0x00212578 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1       0x0021257c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2       0x00212580 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3       0x00212584 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT     0x00212588 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0   0x0021258c /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1   0x00212590 /* Reserved PES State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE0           0x00212594 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE1           0x00212598 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE2           0x0021259c /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE3           0x002125a0 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE4           0x002125a4 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE5           0x002125a8 /* SCD State Register */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0      0x002125ac /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1      0x002125b0 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2      0x002125b4 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3      0x002125b8 /* SCD Reserved State Register */
#define BCHP_XPT_RAVE_XPU_CONFIG                 0x00213000 /* XPU TEST ENABLE REGISTER */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL           0x00213004 /* XPU TEST CONTROL REGISTER */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO    0x00213008 /* XPU TEST CONTROL EXT IO */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0         0x0021300c /* XPU TEST OBSERVE REGISTER */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1         0x00213010 /* XPU TEST OBSERVE REGISTER */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO    0x00213014 /* XPU TEST OBSERVE EXT IO REGISTER */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL   0x00213018 /* RAVE Diagnostics Control Register */
#define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE    0x0021301c /* Stop Packet Count Value */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL 0x00213020 /* AVS SCV Filter mode */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3 0x00213024 /* AVS SCV Filter value 0 to 3 */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7 0x00213028 /* AVS SCV Filter value 4 to 7 */
#define BCHP_XPT_RAVE_AV_STATUS                  0x00213040 /* RAVE Status */
#define BCHP_XPT_RAVE_PACKET_COUNT               0x00213044 /* RAVE input packet counter */
#define BCHP_XPT_RAVE_DATA_START_ADDR_A          0x00213048 /* Pkt and HWA data buffer A base addresses */
#define BCHP_XPT_RAVE_DATA_START_ADDR_B          0x0021304c /* Pkt and HWA data buffer B base addresses */
#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE       0x00213050 /* Watchdog Timer Timeout Value */
#define BCHP_XPT_RAVE_MISC_CONTROL               0x00213058 /* Miscellaneous Control */
#define BCHP_XPT_RAVE_BASE_ADDRESSES             0x0021305c /* Record and SCD Base Addresses */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS         0x00213064 /* Context Hold Status and Clear */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS       0x00213060 /* Band Hold Status and Clear */
#define BCHP_XPT_RAVE_FW_WATERMARK               0x00213068 /* Firmware throughput watermark */
#define BCHP_XPT_RAVE_HW_WATCHDOG                0x0021306c /* Hardware Watchdog Counter */
#define BCHP_XPT_RAVE_MISC_CONTROL2              0x00213070 /* Miscellaneous Control 2 */
#define BCHP_XPT_RAVE_RC0_SP_CONTROL             0x00213080 /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC1_SP_CONTROL             0x00213084 /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC2_SP_CONTROL             0x00213088 /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC3_SP_CONTROL             0x0021308c /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC4_SP_CONTROL             0x00213090 /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC5_SP_CONTROL             0x00213094 /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC6_SP_CONTROL             0x00213098 /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC7_SP_CONTROL             0x0021309c /* Seamless Pause Control */
#define BCHP_XPT_RAVE_RC8_SP_CONTROL             0x002130a0 /* Seamless Pause Control */
#define BCHP_XPT_RAVE_AV_STATUS2                 0x002130a4 /* RAVE Status */
#define BCHP_XPT_RAVE_TM_DMEM                    0x002130b0 /* TM Control */
#define BCHP_XPT_RAVE_TM_IMEM                    0x002130b4 /* TM Control */
#define BCHP_XPT_RAVE_TM_POINTER_RAM             0x002130b8 /* TM Control */
#define BCHP_XPT_RAVE_TM_MUX_BUFFER              0x002130bc /* TM Control */
#define BCHP_XPT_RAVE_TM_CX_TABLE                0x002130c0 /* TM Control */
#define BCHP_XPT_RAVE_TM_CX_TABLE_HI             0x002130c4 /* TM Control */
#define BCHP_XPT_RAVE_TM_SMEM                    0x002130c8 /* TM Control */
#define BCHP_XPT_RAVE_INT_CX0                    0x00213100 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX1                    0x00213104 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX2                    0x00213108 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX3                    0x0021310c /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX4                    0x00213110 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX5                    0x00213114 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX6                    0x00213118 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX7                    0x0021311c /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX8                    0x00213120 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX9                    0x00213124 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX10                   0x00213128 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX11                   0x0021312c /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX12                   0x00213130 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX13                   0x00213134 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX14                   0x00213138 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX15                   0x0021313c /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX16                   0x00213140 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX17                   0x00213144 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX18                   0x00213148 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX19                   0x0021314c /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX20                   0x00213150 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX21                   0x00213154 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX22                   0x00213158 /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_CX23                   0x0021315c /* Context Interrupts */
#define BCHP_XPT_RAVE_INT_MISC                   0x00213160 /* Miscellaneous Interrupts */
#define BCHP_XPT_RAVE_EMM_TID_MODE               0x00216000 /* TPIT EMM_TID_MODE Register (NDS only) */
#define BCHP_XPT_RAVE_EMM_DATA_ID_1              0x00216004 /* TPIT EMM_DATA_ID_1 Register (NDS only) */
#define BCHP_XPT_RAVE_EMM_DATA_ID_2              0x00216008 /* TPIT EMM_DATA_ID_2 Register (NDS only) */
#define BCHP_XPT_RAVE_EMM_DATA_ID_3              0x0021600c /* TPIT EMM_DATA_ID_3 Register (NDS only) */
#define BCHP_XPT_RAVE_EMM_MASK_ID_1              0x00216010 /* TPIT EMM_MASK_ID_1 Register (NDS only) */
#define BCHP_XPT_RAVE_EMM_MASK_ID_2              0x00216014 /* TPIT EMM_MASK_ID_2 Register (NDS only) */
#define BCHP_XPT_RAVE_EMM_MASK_ID_3              0x00216018 /* TPIT EMM_MASK_ID_3 Register (NDS only) */
#define BCHP_XPT_RAVE_TPIT_TIME_TICK             0x00216020 /* TPIT Time Tick Register */
#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT           0x00216024 /* TPIT Time Packet Timeout Register */
#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT           0x00216028 /* TPIT Time Event Timeout Register */
#define BCHP_XPT_RAVE_TPIT0_CTRL1                0x0021a300 /* TPIT 0 Control Register 1 */
#define BCHP_XPT_RAVE_TPIT0_COR1                 0x0021a304 /* TPIT 0 Corrupt Register */
#define BCHP_XPT_RAVE_TPIT0_TID                  0x0021a308 /* TPIT TID Register */
#define BCHP_XPT_RAVE_TPIT0_TID2                 0x0021a30c /* TPIT TID Register 2 */
#define BCHP_XPT_RAVE_TPIT0_STATE0               0x0021a310 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE1               0x0021a314 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE2               0x0021a318 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE2a              0x0021a31c /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE2b              0x0021a320 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE2c              0x0021a324 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE2d              0x0021a328 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE3               0x0021a32c /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE4               0x0021a330 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE5               0x0021a334 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE6               0x0021a338 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE7               0x0021a33c /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE8               0x0021a340 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT0_STATE9               0x0021a344 /* TPIT 0 State Register */
#define BCHP_XPT_RAVE_TPIT1_CTRL1                0x0021a348 /* TPIT 1 Control Register 1 */
#define BCHP_XPT_RAVE_TPIT1_COR1                 0x0021a34c /* TPIT 1 Corrupt Register */
#define BCHP_XPT_RAVE_TPIT1_TID                  0x0021a350 /* TPIT TID Register */
#define BCHP_XPT_RAVE_TPIT1_TID2                 0x0021a354 /* TPIT TID Register 2 */
#define BCHP_XPT_RAVE_TPIT1_STATE0               0x0021a358 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE1               0x0021a35c /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE2               0x0021a360 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE2a              0x0021a364 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE2b              0x0021a368 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE2c              0x0021a36c /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE2d              0x0021a370 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE3               0x0021a374 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE4               0x0021a378 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE5               0x0021a37c /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE6               0x0021a380 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE7               0x0021a384 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE8               0x0021a388 /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT1_STATE9               0x0021a38c /* TPIT 1 State Register */
#define BCHP_XPT_RAVE_TPIT2_CTRL1                0x0021a390 /* TPIT 2 Control Register 1 */
#define BCHP_XPT_RAVE_TPIT2_COR1                 0x0021a394 /* TPIT 2 Corrupt Register */
#define BCHP_XPT_RAVE_TPIT2_TID                  0x0021a398 /* TPIT TID Register */
#define BCHP_XPT_RAVE_TPIT2_TID2                 0x0021a39c /* TPIT TID Register 2 */
#define BCHP_XPT_RAVE_TPIT2_STATE0               0x0021a3a0 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE1               0x0021a3a4 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE2               0x0021a3a8 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE2a              0x0021a3ac /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE2b              0x0021a3b0 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE2c              0x0021a3b4 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE2d              0x0021a3b8 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE3               0x0021a3bc /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE4               0x0021a3c0 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE5               0x0021a3c4 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE6               0x0021a3c8 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE7               0x0021a3cc /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE8               0x0021a3d0 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT2_STATE9               0x0021a3d4 /* TPIT 2 State Register */
#define BCHP_XPT_RAVE_TPIT3_CTRL1                0x0021a3d8 /* TPIT 3 Control Register 1 */
#define BCHP_XPT_RAVE_TPIT3_COR1                 0x0021a3dc /* TPIT 3 Corrupt Register */
#define BCHP_XPT_RAVE_TPIT3_TID                  0x0021a3e0 /* TPIT TID Register */
#define BCHP_XPT_RAVE_TPIT3_TID2                 0x0021a3e4 /* TPIT TID Register 2 */
#define BCHP_XPT_RAVE_TPIT3_STATE0               0x0021a3e8 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE1               0x0021a3ec /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE2               0x0021a3f0 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE2a              0x0021a3f4 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE2b              0x0021a3f8 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE2c              0x0021a3fc /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE2d              0x0021a400 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE3               0x0021a404 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE4               0x0021a408 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE5               0x0021a40c /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE6               0x0021a410 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE7               0x0021a414 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE8               0x0021a418 /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT3_STATE9               0x0021a41c /* TPIT 3 State Register */
#define BCHP_XPT_RAVE_TPIT4_CTRL1                0x0021a420 /* TPIT 4 Control Register 1 */
#define BCHP_XPT_RAVE_TPIT4_COR1                 0x0021a424 /* TPIT 4 Corrupt Register */
#define BCHP_XPT_RAVE_TPIT4_TID                  0x0021a428 /* TPIT TID Register */
#define BCHP_XPT_RAVE_TPIT4_TID2                 0x0021a42c /* TPIT TID Register 2 */
#define BCHP_XPT_RAVE_TPIT4_STATE0               0x0021a430 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE1               0x0021a434 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE2               0x0021a438 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE2a              0x0021a43c /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE2b              0x0021a440 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE2c              0x0021a444 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE2d              0x0021a448 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE3               0x0021a44c /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE4               0x0021a450 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE5               0x0021a454 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE6               0x0021a458 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE7               0x0021a45c /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE8               0x0021a460 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT4_STATE9               0x0021a464 /* TPIT 4 State Register */
#define BCHP_XPT_RAVE_TPIT5_CTRL1                0x0021a468 /* TPIT 5 Control Register 1 */
#define BCHP_XPT_RAVE_TPIT5_COR1                 0x0021a46c /* TPIT 5 Corrupt Register */
#define BCHP_XPT_RAVE_TPIT5_TID                  0x0021a470 /* TPIT TID Register */
#define BCHP_XPT_RAVE_TPIT5_TID2                 0x0021a474 /* TPIT TID Register 2 */
#define BCHP_XPT_RAVE_TPIT5_STATE0               0x0021a478 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE1               0x0021a47c /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE2               0x0021a480 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE2a              0x0021a484 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE2b              0x0021a488 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE2c              0x0021a48c /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE2d              0x0021a490 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE3               0x0021a494 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE4               0x0021a498 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE5               0x0021a49c /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE6               0x0021a4a0 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE7               0x0021a4a4 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE8               0x0021a4a8 /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT5_STATE9               0x0021a4ac /* TPIT 5 State Register */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0        0x0021a4b0 /* TPIT State Register for Context 0 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1        0x0021a4b4 /* TPIT State Register for Context 1 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2        0x0021a4b8 /* TPIT State Register for Context 2 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3        0x0021a4bc /* TPIT State Register for Context 3 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4        0x0021a4c0 /* TPIT State Register for Context 4 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5        0x0021a4c4 /* TPIT State Register for Context 5 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6        0x0021a4c8 /* TPIT State Register for Context 6 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7        0x0021a4cc /* TPIT State Register for Context 7 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8        0x0021a4d0 /* TPIT State Register for Context 8 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9        0x0021a4d4 /* TPIT State Register for Context 9 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10       0x0021a4d8 /* TPIT State Register for Context 10 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11       0x0021a4dc /* TPIT State Register for Context 11 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12       0x0021a4e0 /* TPIT State Register for Context 12 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13       0x0021a4e4 /* TPIT State Register for Context 13 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14       0x0021a4e8 /* TPIT State Register for Context 14 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15       0x0021a4ec /* TPIT State Register for Context 15 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16       0x0021a4f0 /* TPIT State Register for Context 16 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17       0x0021a4f4 /* TPIT State Register for Context 17 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18       0x0021a4f8 /* TPIT State Register for Context 18 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19       0x0021a4fc /* TPIT State Register for Context 19 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20       0x0021a500 /* TPIT State Register for Context 20 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21       0x0021a504 /* TPIT State Register for Context 21 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22       0x0021a508 /* TPIT State Register for Context 22 */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23       0x0021a50c /* TPIT State Register for Context 23 */

/***************************************************************************
 *CX0_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX0_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX0_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX0_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX0_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX0_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX0_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX0_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX0_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX0_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX0_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX0_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX0_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX0_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX0_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX0_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX0_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX0_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX0_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX0_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX0_REC_MISC_CONFIG - Context 0 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX0_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX0_REC_SCD_PIDS_AB - Context 0 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX0_REC_SCD_PIDS_CD - Context 0 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX0_REC_SCD_PIDS_EF - Context 0 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX0_REC_SCD_PIDS_GH - Context 0 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX0_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX0_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX0_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX0_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX0_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX0_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX0_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX0_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX0_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX0_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX0_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX0_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX0_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX0_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX0_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX0_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX0_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX0_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX0_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX0_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX0_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX0_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX0_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX0_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX0_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX0_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX0_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX0_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX0_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX0_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX0_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX0_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX0_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX0_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX0_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX0_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX0_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX0_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX0_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX0_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX0_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX0_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX0_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX0_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX0_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX0_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX0_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX0_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX0_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX0_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX0_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX0_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX0_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX0_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX0_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX0_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX0_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX0_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX0_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX0_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX0_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX0_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX0_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX0_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX0_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX0_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX0_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX0_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX0_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX0_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX0_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX0_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX0_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX0_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX0_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX0_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX1_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX1_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX1_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX1_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX1_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX1_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX1_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX1_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX1_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX1_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX1_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX1_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX1_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX1_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX1_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX1_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX1_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX1_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX1_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX1_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX1_REC_MISC_CONFIG - Context 1 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX1_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX1_REC_SCD_PIDS_AB - Context 1 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX1_REC_SCD_PIDS_CD - Context 1 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX1_REC_SCD_PIDS_EF - Context 1 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX1_REC_SCD_PIDS_GH - Context 1 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX1_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX1_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX1_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX1_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX1_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX1_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX1_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX1_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX1_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX1_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX1_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX1_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX1_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX1_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX1_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX1_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX1_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX1_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX1_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX1_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX1_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX1_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX1_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX1_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX1_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX1_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX1_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX1_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX1_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX1_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX1_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX1_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX1_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX1_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX1_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX1_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX1_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX1_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX1_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX1_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX1_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX1_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX1_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX1_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX1_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX1_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX1_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX1_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX1_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX1_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX1_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX1_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX1_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX1_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX1_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX1_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX1_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX1_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX1_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX1_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX1_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX1_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX1_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX1_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX1_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX1_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX1_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX1_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX1_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX1_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX1_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX1_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX1_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX1_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX1_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX1_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX2_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX2_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX2_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX2_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX2_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX2_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX2_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX2_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX2_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX2_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX2_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX2_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX2_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX2_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX2_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX2_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX2_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX2_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX2_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX2_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX2_REC_MISC_CONFIG - Context 2 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX2_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX2_REC_SCD_PIDS_AB - Context 2 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX2_REC_SCD_PIDS_CD - Context 2 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX2_REC_SCD_PIDS_EF - Context 2 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX2_REC_SCD_PIDS_GH - Context 2 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX2_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX2_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX2_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX2_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX2_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX2_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX2_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX2_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX2_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX2_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX2_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX2_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX2_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX2_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX2_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX2_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX2_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX2_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX2_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX2_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX2_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX2_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX2_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX2_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX2_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX2_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX2_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX2_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX2_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX2_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX2_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX2_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX2_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX2_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX2_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX2_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX2_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX2_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX2_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX2_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX2_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX2_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX2_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX2_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX2_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX2_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX2_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX2_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX2_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX2_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX2_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX2_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX2_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX2_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX2_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX2_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX2_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX2_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX2_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX2_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX2_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX2_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX2_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX2_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX2_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX2_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX2_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX2_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX2_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX2_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX2_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX2_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX2_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX2_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX2_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX2_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX3_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX3_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX3_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX3_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX3_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX3_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX3_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX3_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX3_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX3_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX3_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX3_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX3_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX3_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX3_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX3_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX3_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX3_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX3_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX3_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX3_REC_MISC_CONFIG - Context 3 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX3_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX3_REC_SCD_PIDS_AB - Context 3 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX3_REC_SCD_PIDS_CD - Context 3 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX3_REC_SCD_PIDS_EF - Context 3 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX3_REC_SCD_PIDS_GH - Context 3 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX3_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX3_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX3_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX3_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX3_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX3_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX3_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX3_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX3_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX3_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX3_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX3_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX3_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX3_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX3_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX3_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX3_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX3_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX3_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX3_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX3_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX3_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX3_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX3_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX3_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX3_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX3_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX3_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX3_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX3_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX3_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX3_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX3_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX3_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX3_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX3_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX3_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX3_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX3_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX3_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX3_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX3_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX3_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX3_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX3_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX3_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX3_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX3_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX3_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX3_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX3_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX3_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX3_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX3_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX3_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX3_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX3_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX3_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX3_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX3_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX3_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX3_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX3_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX3_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX3_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX3_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX3_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX3_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX3_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX3_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX3_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX3_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX3_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX3_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX3_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX3_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX4_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX4_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX4_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX4_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX4_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX4_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX4_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX4_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX4_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX4_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX4_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX4_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX4_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX4_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX4_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX4_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX4_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX4_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX4_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX4_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX4_REC_MISC_CONFIG - Context 4 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX4_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX4_REC_SCD_PIDS_AB - Context 4 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX4_REC_SCD_PIDS_CD - Context 4 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX4_REC_SCD_PIDS_EF - Context 4 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX4_REC_SCD_PIDS_GH - Context 4 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX4_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX4_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX4_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX4_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX4_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX4_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX4_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX4_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX4_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX4_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX4_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX4_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX4_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX4_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX4_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX4_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX4_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX4_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX4_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX4_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX4_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX4_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX4_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX4_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX4_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX4_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX4_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX4_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX4_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX4_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX4_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX4_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX4_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX4_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX4_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX4_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX4_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX4_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX4_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX4_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX4_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX4_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX4_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX4_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX4_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX4_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX4_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX4_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX4_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX4_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX4_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX4_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX4_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX4_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX4_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX4_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX4_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX4_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX4_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX4_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX4_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX4_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX4_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX4_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX4_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX4_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX4_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX4_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX4_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX4_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX4_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX4_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX4_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX4_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX4_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX4_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX5_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX5_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX5_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX5_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX5_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX5_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX5_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX5_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX5_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX5_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX5_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX5_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX5_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX5_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX5_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX5_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX5_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX5_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX5_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX5_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX5_REC_MISC_CONFIG - Context 5 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX5_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX5_REC_SCD_PIDS_AB - Context 5 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX5_REC_SCD_PIDS_CD - Context 5 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX5_REC_SCD_PIDS_EF - Context 5 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX5_REC_SCD_PIDS_GH - Context 5 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX5_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX5_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX5_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX5_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX5_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX5_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX5_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX5_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX5_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX5_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX5_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX5_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX5_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX5_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX5_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX5_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX5_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX5_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX5_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX5_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX5_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX5_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX5_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX5_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX5_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX5_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX5_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX5_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX5_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX5_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX5_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX5_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX5_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX5_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX5_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX5_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX5_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX5_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX5_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX5_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX5_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX5_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX5_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX5_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX5_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX5_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX5_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX5_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX5_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX5_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX5_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX5_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX5_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX5_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX5_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX5_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX5_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX5_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX5_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX5_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX5_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX5_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX5_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX5_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX5_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX5_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX5_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX5_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX5_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX5_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX5_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX5_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX5_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX5_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX5_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX5_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX6_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX6_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX6_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX6_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX6_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX6_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX6_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX6_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX6_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX6_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX6_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX6_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX6_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX6_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX6_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX6_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX6_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX6_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX6_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX6_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX6_REC_MISC_CONFIG - Context 6 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX6_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX6_REC_SCD_PIDS_AB - Context 6 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX6_REC_SCD_PIDS_CD - Context 6 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX6_REC_SCD_PIDS_EF - Context 6 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX6_REC_SCD_PIDS_GH - Context 6 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX6_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX6_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX6_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX6_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX6_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX6_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX6_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX6_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX6_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX6_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX6_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX6_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX6_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX6_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX6_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX6_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX6_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX6_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX6_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX6_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX6_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX6_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX6_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX6_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX6_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX6_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX6_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX6_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX6_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX6_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX6_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX6_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX6_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX6_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX6_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX6_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX6_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX6_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX6_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX6_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX6_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX6_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX6_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX6_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX6_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX6_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX6_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX6_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX6_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX6_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX6_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX6_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX6_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX6_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX6_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX6_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX6_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX6_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX6_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX6_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX6_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX6_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX6_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX6_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX6_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX6_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX6_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX6_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX6_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX6_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX6_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX6_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX6_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX6_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX6_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX6_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX7_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX7_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX7_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX7_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX7_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX7_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX7_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX7_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX7_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX7_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX7_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX7_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX7_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX7_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX7_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX7_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX7_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX7_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX7_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX7_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX7_REC_MISC_CONFIG - Context 7 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX7_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX7_REC_SCD_PIDS_AB - Context 7 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX7_REC_SCD_PIDS_CD - Context 7 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX7_REC_SCD_PIDS_EF - Context 7 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX7_REC_SCD_PIDS_GH - Context 7 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX7_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX7_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX7_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX7_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX7_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX7_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX7_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX7_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX7_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX7_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX7_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX7_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX7_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX7_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX7_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX7_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX7_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX7_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX7_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX7_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX7_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX7_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX7_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX7_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX7_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX7_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX7_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX7_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX7_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX7_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX7_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX7_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX7_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX7_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX7_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX7_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX7_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX7_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX7_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX7_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX7_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX7_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX7_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX7_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX7_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX7_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX7_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX7_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX7_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX7_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX7_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX7_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX7_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX7_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX7_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX7_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX7_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX7_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX7_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX7_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX7_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX7_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX7_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX7_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX7_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX7_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX7_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX7_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX7_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX7_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX7_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX7_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX7_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX7_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX7_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX7_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX8_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX8_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX8_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX8_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX8_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX8_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX8_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX8_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX8_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX8_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX8_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX8_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX8_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX8_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX8_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX8_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX8_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX8_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX8_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX8_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX8_REC_MISC_CONFIG - Context 8 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX8_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX8_REC_SCD_PIDS_AB - Context 8 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX8_REC_SCD_PIDS_CD - Context 8 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX8_REC_SCD_PIDS_EF - Context 8 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX8_REC_SCD_PIDS_GH - Context 8 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX8_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX8_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX8_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX8_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX8_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX8_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX8_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX8_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX8_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX8_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX8_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX8_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX8_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX8_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX8_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX8_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX8_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX8_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX8_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX8_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX8_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX8_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX8_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX8_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX8_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX8_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX8_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX8_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX8_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX8_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX8_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX8_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX8_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX8_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX8_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX8_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX8_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX8_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX8_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX8_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX8_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX8_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX8_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX8_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX8_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX8_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX8_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX8_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX8_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX8_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX8_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX8_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX8_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX8_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX8_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX8_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX8_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX8_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX8_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX8_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX8_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX8_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX8_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX8_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX8_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX8_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX8_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX8_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX8_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX8_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX8_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX8_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX8_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX8_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX8_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX8_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX9_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX9_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR_CDB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX9_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX9_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR_CDB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR_CDB_END_PTR_SHIFT         0

/***************************************************************************
 *CX9_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX9_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX9_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX9_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX9_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX9_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX9_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX9_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT     0

/***************************************************************************
 *CX9_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR_ITB_READ_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT       0

/***************************************************************************
 *CX9_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT       0

/***************************************************************************
 *CX9_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR_ITB_END_PTR_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR_ITB_END_PTR_SHIFT         0

/***************************************************************************
 *CX9_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK      0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT     0

/***************************************************************************
 *CX9_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX9_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX9_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX9_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK         0x80000000
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT        31

/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_OVERFLOW_MASK           0x40000000
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT          30

/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK    0x30000000
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT   28

/* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK       0x0fffffff
#define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT      0

/***************************************************************************
 *CX9_REC_MISC_CONFIG - Context 9 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco0_MASK   0xfffe0000
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco0_SHIFT  17

/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK   0x00008000
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT  15

/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_REC_AVN_MASK             0x00004000
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_REC_AVN_SHIFT            14

/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_ENABLE_MASK         0x00002000
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT        13

/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_CHANNEL_MASK        0x00001f00
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT       8

/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco1_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco1_SHIFT  2

/* XPT_RAVE :: CX9_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SCD_MAP_MODE_MASK        0x00000003
#define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT       0

/***************************************************************************
 *CX9_REC_SCD_PIDS_AB - Context 9 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX9_REC_SCD_PIDS_CD - Context 9 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX9_REC_SCD_PIDS_EF - Context 9 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX9_REC_SCD_PIDS_GH - Context 9 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX9_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT       31

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_SHIFT_PTS_MASK           0x20000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT          29

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONVERT_PTS_MASK         0x10000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT        28

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK       0x0c000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT      26

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK       0x03000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT      24

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK       0x00800000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT      23

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK       0x00600000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT      21

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK      0x00100000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT     20

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK     0x000f0000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT    16

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_HI_MASK        0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT       8

/* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_LO_MASK        0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT       0

/***************************************************************************
 *CX9_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK  0x80000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco0_MASK   0x7fc00000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT  22

/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK     0x00200000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT    21

/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK     0x00100000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT    20

/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco1_MASK   0x000ff800
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT  11

/* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK   0x000007ff
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT  0

/***************************************************************************
 *CX9_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK  0xff000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_reserved_for_eco0_MASK   0x00008000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT  15

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK   0x00002000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT  13

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK  0x00001000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK  0x00000100
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK  0x00000080
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK    0x00000040
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT   6

/* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX9_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_reserved0_MASK      0xfffff000
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_reserved0_SHIFT     12

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK  0x00000040
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK     0x00200000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT    21

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK  0x000e0000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco0_MASK  0xf8000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK       0x04000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT      26

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK    0x02000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT   25

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK   0x00400000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT  22

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco1_MASK  0x00200000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK  0x00100000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco2_MASK  0x00080000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK  0x00060000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_REPEAT_BYTE_MASK        0x0001e000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT       13

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMP_ENABLE_MASK        0x00001000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT       12

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK  0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK  0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK  0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK  0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX9_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX9_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK     0x80000000
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT    31

/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PID_VALID_MASK          0x40000000
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PID_VALID_SHIFT         30

/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK     0x3c000000
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT    26

/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SSID_ENABLE_MASK        0x02000000
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT       25

/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SPLICE_EN_MASK          0x01000000
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SPLICE_EN_SHIFT         24

/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_reserved_for_eco0_MASK  0x00e00000
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_BAND_NUM_MASK           0x001f0000
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_BAND_NUM_SHIFT          16

/* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX9_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco0_MASK         0xffff0000
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco0_SHIFT        16

/* XPT_RAVE :: CX9_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV2MPEG_PADNUM_MASK           0x0000ff00
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT          8

/* XPT_RAVE :: CX9_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco1_MASK         0x000000c0
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco1_SHIFT        6

/* XPT_RAVE :: CX9_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_ATSC_SCRAM_CTRL_MASK           0x00000020
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT          5

/* XPT_RAVE :: CX9_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_PARSE_SC_MASK                  0x00000010
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_PARSE_SC_SHIFT                 4

/* XPT_RAVE :: CX9_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK       0x00000008
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT      3

/* XPT_RAVE :: CX9_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK         0x00000004
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT        2

/* XPT_RAVE :: CX9_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_DTV2MPG_EN_MASK            0x00000002
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_DTV2MPG_EN_SHIFT           1

/* XPT_RAVE :: CX9_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK      0x00000001
#define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT     0

/***************************************************************************
 *CX9_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX9_REC_INIT_TS_INIT_TS_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX9_REC_INIT_TS_INIT_TS_SHIFT                0

/***************************************************************************
 *CX9_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_reserved_for_eco0_MASK       0xffffffc0
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_reserved_for_eco0_SHIFT      6

/* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_CHECK_DIS_MASK            0x00000020
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_CHECK_DIS_SHIFT           5

/* XPT_RAVE :: CX9_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK      0x00000018
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT     3

/* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_INIT_EN_MASK              0x00000004
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_INIT_EN_SHIFT             2

/* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_USER_BITS_MASK            0x00000003
#define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_USER_BITS_SHIFT           0

/***************************************************************************
 *CX9_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_reserved_for_eco0_MASK   0xfe000000
#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_reserved_for_eco0_SHIFT  25

/* XPT_RAVE :: CX9_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_COUNT_MODE_MASK      0x01000000
#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT     24

/* XPT_RAVE :: CX9_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK     0x00ffffff
#define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT    0

/***************************************************************************
 *CX9_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK     0xff000000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT    24

/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco0_MASK   0x00800000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT  23

/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK     0x007f0000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT    16

/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco1_MASK   0x00008000
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT  15

/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK     0x00007f00
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT    8

/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco2_MASK   0x000000fc
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT  2

/* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK    0x00000003
#define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT   0

/***************************************************************************
 *CX9_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX9_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_CX9_PIC_CTR_reserved0_SHIFT                  16

/* XPT_RAVE :: CX9_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_VALUE_MASK                       0x0000ffff
#define BCHP_XPT_RAVE_CX9_PIC_CTR_VALUE_SHIFT                      0

/***************************************************************************
 *CX9_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved0_MASK              0x80000000
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved0_SHIFT             31

/* XPT_RAVE :: CX9_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK    0x70000000
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT   28

/* XPT_RAVE :: CX9_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_EN_MASK             0x08000000
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_EN_SHIFT            27

/* XPT_RAVE :: CX9_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved1_MASK              0x04000000
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved1_SHIFT             26

/* XPT_RAVE :: CX9_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_MODE_MASK           0x03000000
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT          24

/* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV0_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV0_SHIFT                  16

/* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV1_MASK                   0x0000ff00
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV1_SHIFT                  8

/* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV2_MASK                   0x000000ff
#define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV2_SHIFT                  0

/***************************************************************************
 *CX9_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX9_REC_TIMER_REC_TIMER_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX9_REC_TIMER_REC_TIMER_SHIFT                0

/***************************************************************************
 *CX9_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco0_MASK        0xfffc0000
#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco0_SHIFT       18

/* XPT_RAVE :: CX9_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INIT_TIME_LO_MASK         0x0003ff00
#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INIT_TIME_LO_SHIFT        8

/* XPT_RAVE :: CX9_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco1_MASK        0x000000f0
#define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco1_SHIFT       4

/* XPT_RAVE :: CX9_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX9_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK  0x0000000c
#define BCHP_XPT_RAVE_CX9_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX9_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX9_REC_STATE0_TS_INITIALIZED_MASK           0x00000002
#define BCHP_XPT_RAVE_CX9_REC_STATE0_TS_INITIALIZED_SHIFT          1

/* XPT_RAVE :: CX9_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INITIALIZED_MASK          0x00000001
#define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INITIALIZED_SHIFT         0

/***************************************************************************
 *CX9_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX9_REC_STATE1_REC_INIT_TIME_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX9_REC_STATE1_REC_INIT_TIME_HI_SHIFT        0

/***************************************************************************
 *CX9_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX9_REC_STATE2_INT_TIME_STAMP_MASK           0xffffffff
#define BCHP_XPT_RAVE_CX9_REC_STATE2_INT_TIME_STAMP_SHIFT          0

/***************************************************************************
 *CX9_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX9_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX9_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX9_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX9_REC_STATE3_reserved_for_eco0_MASK        0xfffffe00
#define BCHP_XPT_RAVE_CX9_REC_STATE3_reserved_for_eco0_SHIFT       9

/* XPT_RAVE :: CX9_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_DSS_PARITY_MASK           0x00000100
#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_DSS_PARITY_SHIFT          8

/* XPT_RAVE :: CX9_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_COUNT_HI_MASK             0x000000ff
#define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_COUNT_HI_SHIFT            0

/***************************************************************************
 *CX9_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX9_REC_COUNT_REC_COUNT_MASK                 0xffffffff
#define BCHP_XPT_RAVE_CX9_REC_COUNT_REC_COUNT_SHIFT                0

/***************************************************************************
 *CX9_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_reserved0_MASK          0xfffc0000
#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_reserved0_SHIFT         18

/* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK       0x00030000
#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT      16

/* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK      0x0000ffff
#define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT     0

/***************************************************************************
 *CX9_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX9_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX9_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX9_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_0_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_0_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX9_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX9_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_1_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_1_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX9_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX9_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_2_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_2_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX9_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX9_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_3_reserved_for_eco0_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX9_RAVE_Reg_3_reserved_for_eco0_SHIFT       0

/***************************************************************************
 *CX10_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX10_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX10_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX10_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX10_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX10_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX10_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX10_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX10_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX10_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX10_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX10_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX10_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX10_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX10_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX10_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX10_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX10_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX10_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX10_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX10_REC_MISC_CONFIG - Context 10 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX10_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX10_REC_SCD_PIDS_AB - Context 10 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX10_REC_SCD_PIDS_CD - Context 10 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX10_REC_SCD_PIDS_EF - Context 10 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX10_REC_SCD_PIDS_GH - Context 10 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX10_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX10_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX10_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX10_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX10_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX10_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX10_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX10_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX10_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX10_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX10_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX10_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX10_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX10_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX10_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX10_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX10_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX10_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX10_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX10_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX10_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX10_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX10_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX10_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX10_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX10_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX10_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX10_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX10_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX10_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX10_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX10_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX10_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX10_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX10_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX10_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX10_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX10_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX10_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX10_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX10_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX10_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX10_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX10_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX10_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX10_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX10_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX10_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX10_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX10_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX10_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX10_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX10_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX10_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX10_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX10_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX10_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX10_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX10_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX10_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX10_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX10_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX10_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX10_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX10_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX10_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX10_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX10_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX10_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX10_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX10_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX10_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX10_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX10_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX10_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX10_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX11_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX11_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX11_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX11_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX11_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX11_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX11_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX11_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX11_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX11_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX11_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX11_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX11_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX11_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX11_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX11_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX11_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX11_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX11_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX11_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX11_REC_MISC_CONFIG - Context 11 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX11_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX11_REC_SCD_PIDS_AB - Context 11 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX11_REC_SCD_PIDS_CD - Context 11 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX11_REC_SCD_PIDS_EF - Context 11 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX11_REC_SCD_PIDS_GH - Context 11 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX11_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX11_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX11_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX11_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX11_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX11_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX11_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX11_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX11_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX11_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX11_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX11_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX11_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX11_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX11_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX11_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX11_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX11_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX11_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX11_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX11_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX11_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX11_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX11_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX11_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX11_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX11_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX11_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX11_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX11_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX11_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX11_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX11_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX11_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX11_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX11_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX11_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX11_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX11_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX11_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX11_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX11_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX11_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX11_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX11_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX11_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX11_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX11_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX11_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX11_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX11_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX11_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX11_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX11_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX11_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX11_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX11_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX11_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX11_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX11_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX11_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX11_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX11_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX11_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX11_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX11_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX11_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX11_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX11_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX11_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX11_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX11_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX11_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX11_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX11_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX11_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX12_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX12_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX12_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX12_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX12_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX12_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX12_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX12_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX12_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX12_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX12_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX12_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX12_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX12_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX12_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX12_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX12_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX12_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX12_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX12_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX12_REC_MISC_CONFIG - Context 12 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX12_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX12_REC_SCD_PIDS_AB - Context 12 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX12_REC_SCD_PIDS_CD - Context 12 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX12_REC_SCD_PIDS_EF - Context 12 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX12_REC_SCD_PIDS_GH - Context 12 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX12_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX12_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX12_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX12_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX12_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX12_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX12_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX12_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX12_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX12_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX12_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX12_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX12_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX12_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX12_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX12_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX12_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX12_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX12_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX12_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX12_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX12_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX12_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX12_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX12_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX12_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX12_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX12_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX12_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX12_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX12_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX12_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX12_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX12_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX12_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX12_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX12_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX12_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX12_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX12_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX12_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX12_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX12_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX12_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX12_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX12_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX12_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX12_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX12_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX12_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX12_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX12_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX12_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX12_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX12_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX12_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX12_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX12_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX12_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX12_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX12_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX12_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX12_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX12_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX12_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX12_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX12_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX12_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX12_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX12_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX12_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX12_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX12_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX12_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX12_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX12_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX13_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX13_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX13_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX13_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX13_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX13_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX13_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX13_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX13_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX13_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX13_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX13_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX13_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX13_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX13_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX13_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX13_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX13_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX13_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX13_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX13_REC_MISC_CONFIG - Context 13 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX13_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX13_REC_SCD_PIDS_AB - Context 13 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX13_REC_SCD_PIDS_CD - Context 13 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX13_REC_SCD_PIDS_EF - Context 13 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX13_REC_SCD_PIDS_GH - Context 13 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX13_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX13_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX13_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX13_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX13_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX13_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX13_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX13_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX13_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX13_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX13_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX13_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX13_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX13_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX13_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX13_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX13_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX13_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX13_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX13_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX13_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX13_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX13_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX13_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX13_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX13_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX13_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX13_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX13_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX13_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX13_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX13_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX13_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX13_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX13_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX13_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX13_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX13_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX13_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX13_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX13_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX13_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX13_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX13_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX13_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX13_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX13_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX13_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX13_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX13_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX13_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX13_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX13_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX13_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX13_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX13_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX13_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX13_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX13_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX13_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX13_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX13_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX13_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX13_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX13_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX13_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX13_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX13_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX13_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX13_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX13_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX13_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX13_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX13_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX13_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX13_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX14_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX14_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX14_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX14_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX14_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX14_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX14_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX14_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX14_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX14_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX14_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX14_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX14_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX14_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX14_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX14_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX14_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX14_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX14_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX14_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX14_REC_MISC_CONFIG - Context 14 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX14_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX14_REC_SCD_PIDS_AB - Context 14 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX14_REC_SCD_PIDS_CD - Context 14 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX14_REC_SCD_PIDS_EF - Context 14 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX14_REC_SCD_PIDS_GH - Context 14 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX14_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX14_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX14_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX14_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX14_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX14_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX14_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX14_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX14_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX14_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX14_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX14_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX14_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX14_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX14_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX14_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX14_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX14_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX14_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX14_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX14_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX14_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX14_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX14_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX14_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX14_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX14_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX14_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX14_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX14_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX14_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX14_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX14_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX14_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX14_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX14_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX14_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX14_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX14_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX14_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX14_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX14_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX14_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX14_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX14_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX14_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX14_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX14_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX14_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX14_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX14_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX14_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX14_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX14_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX14_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX14_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX14_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX14_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX14_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX14_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX14_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX14_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX14_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX14_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX14_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX14_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX14_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX14_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX14_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX14_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX14_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX14_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX14_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX14_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX14_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX14_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX15_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX15_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX15_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX15_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX15_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX15_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX15_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX15_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX15_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX15_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX15_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX15_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX15_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX15_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX15_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX15_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX15_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX15_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX15_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX15_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX15_REC_MISC_CONFIG - Context 15 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX15_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX15_REC_SCD_PIDS_AB - Context 15 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX15_REC_SCD_PIDS_CD - Context 15 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX15_REC_SCD_PIDS_EF - Context 15 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX15_REC_SCD_PIDS_GH - Context 15 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX15_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX15_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX15_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX15_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX15_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX15_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX15_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX15_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX15_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX15_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX15_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX15_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX15_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX15_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX15_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX15_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX15_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX15_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX15_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX15_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX15_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX15_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX15_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX15_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX15_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX15_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX15_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX15_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX15_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX15_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX15_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX15_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX15_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX15_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX15_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX15_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX15_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX15_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX15_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX15_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX15_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX15_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX15_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX15_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX15_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX15_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX15_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX15_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX15_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX15_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX15_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX15_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX15_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX15_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX15_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX15_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX15_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX15_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX15_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX15_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX15_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX15_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX15_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX15_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX15_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX15_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX15_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX15_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX15_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX15_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX15_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX15_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX15_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX15_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX15_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX15_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX16_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX16_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX16_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX16_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX16_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX16_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX16_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX16_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX16_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX16_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX16_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX16_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX16_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX16_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX16_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX16_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX16_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX16_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX16_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX16_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX16_REC_MISC_CONFIG - Context 16 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX16_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX16_REC_SCD_PIDS_AB - Context 16 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX16_REC_SCD_PIDS_CD - Context 16 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX16_REC_SCD_PIDS_EF - Context 16 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX16_REC_SCD_PIDS_GH - Context 16 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX16_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX16_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX16_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX16_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX16_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX16_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX16_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX16_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX16_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX16_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX16_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX16_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX16_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX16_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX16_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX16_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX16_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX16_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX16_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX16_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX16_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX16_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX16_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX16_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX16_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX16_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX16_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX16_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX16_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX16_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX16_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX16_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX16_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX16_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX16_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX16_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX16_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX16_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX16_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX16_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX16_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX16_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX16_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX16_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX16_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX16_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX16_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX16_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX16_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX16_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX16_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX16_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX16_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX16_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX16_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX16_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX16_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX16_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX16_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX16_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX16_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX16_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX16_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX16_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX16_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX16_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX16_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX16_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX16_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX16_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX16_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX16_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX16_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX16_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX16_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX16_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX17_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX17_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX17_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX17_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX17_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX17_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX17_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX17_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX17_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX17_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX17_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX17_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX17_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX17_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX17_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX17_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX17_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX17_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX17_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX17_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX17_REC_MISC_CONFIG - Context 17 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX17_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX17_REC_SCD_PIDS_AB - Context 17 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX17_REC_SCD_PIDS_CD - Context 17 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX17_REC_SCD_PIDS_EF - Context 17 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX17_REC_SCD_PIDS_GH - Context 17 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX17_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX17_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX17_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX17_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX17_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX17_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX17_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX17_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX17_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX17_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX17_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX17_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX17_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX17_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX17_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX17_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX17_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX17_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX17_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX17_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX17_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX17_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX17_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX17_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX17_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX17_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX17_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX17_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX17_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX17_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX17_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX17_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX17_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX17_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX17_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX17_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX17_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX17_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX17_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX17_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX17_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX17_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX17_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX17_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX17_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX17_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX17_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX17_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX17_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX17_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX17_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX17_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX17_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX17_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX17_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX17_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX17_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX17_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX17_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX17_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX17_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX17_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX17_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX17_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX17_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX17_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX17_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX17_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX17_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX17_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX17_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX17_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX17_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX17_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX17_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX17_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX18_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX18_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX18_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX18_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX18_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX18_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX18_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX18_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX18_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX18_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX18_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX18_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX18_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX18_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX18_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX18_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX18_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX18_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX18_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX18_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX18_REC_MISC_CONFIG - Context 18 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX18_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX18_REC_SCD_PIDS_AB - Context 18 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX18_REC_SCD_PIDS_CD - Context 18 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX18_REC_SCD_PIDS_EF - Context 18 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX18_REC_SCD_PIDS_GH - Context 18 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX18_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX18_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX18_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX18_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX18_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX18_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX18_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX18_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX18_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX18_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX18_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX18_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX18_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX18_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX18_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX18_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX18_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX18_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX18_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX18_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX18_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX18_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX18_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX18_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX18_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX18_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX18_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX18_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX18_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX18_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX18_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX18_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX18_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX18_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX18_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX18_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX18_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX18_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX18_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX18_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX18_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX18_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX18_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX18_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX18_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX18_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX18_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX18_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX18_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX18_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX18_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX18_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX18_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX18_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX18_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX18_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX18_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX18_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX18_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX18_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX18_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX18_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX18_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX18_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX18_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX18_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX18_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX18_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX18_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX18_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX18_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX18_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX18_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX18_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX18_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX18_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX19_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX19_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX19_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX19_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX19_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX19_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX19_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX19_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX19_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX19_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX19_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX19_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX19_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX19_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX19_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX19_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX19_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX19_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX19_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX19_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX19_REC_MISC_CONFIG - Context 19 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX19_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX19_REC_SCD_PIDS_AB - Context 19 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX19_REC_SCD_PIDS_CD - Context 19 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX19_REC_SCD_PIDS_EF - Context 19 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX19_REC_SCD_PIDS_GH - Context 19 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX19_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX19_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX19_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX19_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX19_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX19_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX19_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX19_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX19_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX19_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX19_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX19_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX19_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX19_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX19_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX19_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX19_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX19_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX19_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX19_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX19_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX19_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX19_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX19_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX19_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX19_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX19_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX19_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX19_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX19_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX19_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX19_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX19_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX19_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX19_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX19_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX19_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX19_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX19_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX19_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX19_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX19_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX19_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX19_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX19_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX19_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX19_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX19_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX19_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX19_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX19_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX19_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX19_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX19_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX19_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX19_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX19_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX19_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX19_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX19_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX19_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX19_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX19_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX19_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX19_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX19_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX19_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX19_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX19_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX19_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX19_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX19_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX19_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX19_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX19_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX19_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX20_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX20_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX20_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX20_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX20_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX20_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX20_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX20_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX20_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX20_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX20_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX20_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX20_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX20_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX20_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX20_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX20_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX20_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX20_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX20_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX20_REC_MISC_CONFIG - Context 20 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX20_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX20_REC_SCD_PIDS_AB - Context 20 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX20_REC_SCD_PIDS_CD - Context 20 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX20_REC_SCD_PIDS_EF - Context 20 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX20_REC_SCD_PIDS_GH - Context 20 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX20_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX20_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX20_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX20_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX20_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX20_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX20_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX20_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX20_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX20_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX20_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX20_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX20_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX20_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX20_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX20_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX20_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX20_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX20_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX20_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX20_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX20_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX20_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX20_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX20_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX20_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX20_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX20_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX20_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX20_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX20_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX20_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX20_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX20_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX20_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX20_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX20_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX20_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX20_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX20_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX20_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX20_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX20_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX20_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX20_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX20_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX20_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX20_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX20_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX20_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX20_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX20_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX20_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX20_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX20_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX20_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX20_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX20_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX20_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX20_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX20_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX20_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX20_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX20_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX20_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX20_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX20_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX20_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX20_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX20_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX20_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX20_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX20_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX20_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX20_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX20_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX21_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX21_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX21_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX21_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX21_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX21_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX21_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX21_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX21_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX21_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX21_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX21_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX21_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX21_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX21_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX21_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX21_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX21_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX21_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX21_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX21_REC_MISC_CONFIG - Context 21 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX21_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX21_REC_SCD_PIDS_AB - Context 21 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX21_REC_SCD_PIDS_CD - Context 21 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX21_REC_SCD_PIDS_EF - Context 21 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX21_REC_SCD_PIDS_GH - Context 21 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX21_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX21_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX21_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX21_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX21_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX21_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX21_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX21_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX21_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX21_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX21_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX21_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX21_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX21_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX21_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX21_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX21_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX21_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX21_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX21_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX21_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX21_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX21_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX21_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX21_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX21_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX21_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX21_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX21_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX21_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX21_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX21_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX21_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX21_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX21_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX21_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX21_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX21_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX21_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX21_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX21_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX21_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX21_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX21_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX21_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX21_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX21_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX21_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX21_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX21_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX21_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX21_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX21_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX21_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX21_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX21_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX21_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX21_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX21_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX21_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX21_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX21_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX21_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX21_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX21_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX21_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX21_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX21_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX21_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX21_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX21_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX21_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX21_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX21_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX21_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX21_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX22_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX22_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX22_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX22_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX22_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX22_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX22_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX22_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX22_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX22_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX22_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX22_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX22_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX22_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX22_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX22_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX22_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX22_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX22_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX22_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX22_REC_MISC_CONFIG - Context 22 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX22_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX22_REC_SCD_PIDS_AB - Context 22 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX22_REC_SCD_PIDS_CD - Context 22 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX22_REC_SCD_PIDS_EF - Context 22 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX22_REC_SCD_PIDS_GH - Context 22 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX22_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX22_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX22_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX22_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX22_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX22_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX22_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX22_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX22_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX22_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX22_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX22_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX22_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX22_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX22_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX22_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX22_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX22_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX22_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX22_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX22_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX22_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX22_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX22_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX22_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX22_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX22_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX22_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX22_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX22_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX22_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX22_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX22_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX22_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX22_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX22_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX22_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX22_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX22_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX22_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX22_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX22_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX22_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX22_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX22_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX22_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX22_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX22_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX22_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX22_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX22_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX22_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX22_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX22_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX22_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX22_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX22_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX22_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX22_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX22_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX22_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX22_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX22_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX22_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX22_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX22_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX22_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX22_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX22_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX22_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX22_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX22_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX22_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX22_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX22_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX22_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX23_AV_CDB_WRITE_PTR - Context CDB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX23_AV_CDB_READ_PTR - Context CDB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR_CDB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX23_AV_CDB_BASE_PTR - Context CDB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX23_AV_CDB_END_PTR - Context CDB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR_CDB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR_CDB_END_PTR_SHIFT        0

/***************************************************************************
 *CX23_AV_CDB_VALID_PTR - Context CDB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX23_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX23_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX23_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX23_AV_CDB_DEPTH - Context CDB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX23_AV_THRESHOLDS - Context Thresholds
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX23_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX23_AV_ITB_WRITE_PTR - Context ITB Write Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT    0

/***************************************************************************
 *CX23_AV_ITB_READ_PTR - Context ITB Read Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR_ITB_READ_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT      0

/***************************************************************************
 *CX23_AV_ITB_BASE_PTR - Context ITB Base Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT      0

/***************************************************************************
 *CX23_AV_ITB_END_PTR - Context ITB End Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR_ITB_END_PTR_MASK         0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR_ITB_END_PTR_SHIFT        0

/***************************************************************************
 *CX23_AV_ITB_VALID_PTR - Context ITB Valid Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK     0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT    0

/***************************************************************************
 *CX23_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0

/***************************************************************************
 *CX23_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000
#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16

/* XPT_RAVE :: CX23_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0

/***************************************************************************
 *CX23_AV_ITB_DEPTH - Context ITB Depth
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK        0x80000000
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT       31

/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_OVERFLOW_MASK          0x40000000
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT         30

/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK   0x30000000
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT  28

/* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK      0x0fffffff
#define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT     0

/***************************************************************************
 *CX23_REC_MISC_CONFIG - Context 23 Miscellaneous Config
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco0_MASK  0xfffe0000
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17

/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16

/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK  0x00008000
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15

/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: REC_AVN [14:14] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_REC_AVN_MASK            0x00004000
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_REC_AVN_SHIFT           14

/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_ENABLE_MASK        0x00002000
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT       13

/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_CHANNEL_MASK       0x00001f00
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT      8

/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco1_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2

/* XPT_RAVE :: CX23_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SCD_MAP_MODE_MASK       0x00000003
#define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT      0

/***************************************************************************
 *CX23_REC_SCD_PIDS_AB - Context 23 SCD map PIDS A and B
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0

/***************************************************************************
 *CX23_REC_SCD_PIDS_CD - Context 23 SCD map PIDS C and D
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0

/***************************************************************************
 *CX23_REC_SCD_PIDS_EF - Context 23 SCD map PIDS E and F
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0

/***************************************************************************
 *CX23_REC_SCD_PIDS_GH - Context 23 SCD map PIDS G and H
 ***************************************************************************/
/* union - case Mapped_SCD_via_PID_channels [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0

/* union - case Mapped_SCD_via_stream_PID_values [31:00] */
/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13

/* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff
#define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0

/***************************************************************************
 *CX23_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK       0x80000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT      31

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_SHIFT_PTS_MASK          0x20000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT         29

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONVERT_PTS_MASK        0x10000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT       28

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK      0x0c000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT     26

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK      0x03000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT     24

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK      0x00800000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT     23

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK      0x00600000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT     21

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK     0x00100000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT    20

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK    0x000f0000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT   16

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_HI_MASK       0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT      8

/* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_LO_MASK       0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT      0

/***************************************************************************
 *CX23_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31

/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco0_MASK  0x7fc00000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22

/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK    0x00200000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT   21

/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK    0x00100000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT   20

/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco1_MASK  0x000ff800
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11

/* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *CX23_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_reserved_for_eco0_MASK  0x00008000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK  0x00002000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK   0x00000040
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT  6

/* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0

/***************************************************************************
 *CX23_AV_INTERRUPT_ENABLES - Context Interrupt Enables
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_reserved0_MASK     0xfffff000
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_reserved0_SHIFT    12

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1

/* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001
#define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP1_CONTROL - Context Comparator 1 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK    0x00200000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT   21

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP2_CONTROL - Context Comparator 2 Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK      0x04000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT     26

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK   0x02000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT  25

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK  0x00400000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_REPEAT_BYTE_MASK       0x0001e000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT      13

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMP_ENABLE_MASK       0x00001000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT      12

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7

/* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f
#define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24

/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16

/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8

/* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24

/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16

/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8

/* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value
 ***************************************************************************/
/* union - case Exclusion_Value_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24

/* union - case Exclusion_Value_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16

/* union - case Exclusion_Value_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8

/* union - case Exclusion_Value_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* union - case Exclusion_Mask_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24

/* union - case Inclusion_Range_D [31:24] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24

/* union - case Exclusion_Mask_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16

/* union - case Inclusion_Range_C [23:16] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16

/* union - case Exclusion_Mask_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8

/* union - case Inclusion_Range_B [15:08] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8

/* union - case Exclusion_Mask_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0

/* union - case Inclusion_Range_A [07:00] */
/* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff
#define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0

/***************************************************************************
 *CX23_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2

/* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003
#define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0

/***************************************************************************
 *CX23_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK    0x80000000
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT   31

/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: PID_VALID [30:30] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PID_VALID_MASK         0x40000000
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PID_VALID_SHIFT        30

/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK    0x3c000000
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT   26

/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SSID_ENABLE_MASK       0x02000000
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT      25

/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SPLICE_EN_MASK         0x01000000
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SPLICE_EN_SHIFT        24

/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21

/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: BAND_NUM [20:16] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_BAND_NUM_MASK          0x001f0000
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_BAND_NUM_SHIFT         16

/* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff
#define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0

/***************************************************************************
 *CX23_REC_CTRL1 - Record Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_CTRL1 :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco0_MASK        0xffff0000
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco0_SHIFT       16

/* XPT_RAVE :: CX23_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV2MPEG_PADNUM_MASK          0x0000ff00
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT         8

/* XPT_RAVE :: CX23_REC_CTRL1 :: reserved_for_eco1 [07:06] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco1_MASK        0x000000c0
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco1_SHIFT       6

/* XPT_RAVE :: CX23_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_ATSC_SCRAM_CTRL_MASK          0x00000020
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT         5

/* XPT_RAVE :: CX23_REC_CTRL1 :: PARSE_SC [04:04] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_PARSE_SC_MASK                 0x00000010
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_PARSE_SC_SHIFT                4

/* XPT_RAVE :: CX23_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK      0x00000008
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT     3

/* XPT_RAVE :: CX23_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK        0x00000004
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT       2

/* XPT_RAVE :: CX23_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_DTV2MPG_EN_MASK           0x00000002
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_DTV2MPG_EN_SHIFT          1

/* XPT_RAVE :: CX23_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK     0x00000001
#define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT    0

/***************************************************************************
 *CX23_REC_INIT_TS - Record Initial Timestamp Value Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_INIT_TS :: INIT_TS [31:00] */
#define BCHP_XPT_RAVE_CX23_REC_INIT_TS_INIT_TS_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX23_REC_INIT_TS_INIT_TS_SHIFT               0

/***************************************************************************
 *CX23_REC_TS_CTRL - Record Timestamp Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_TS_CTRL :: reserved_for_eco0 [31:06] */
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_reserved_for_eco0_MASK      0xffffffc0
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_reserved_for_eco0_SHIFT     6

/* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_CHECK_DIS_MASK           0x00000020
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_CHECK_DIS_SHIFT          5

/* XPT_RAVE :: CX23_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK     0x00000018
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT    3

/* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_INIT_EN [02:02] */
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_INIT_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_INIT_EN_SHIFT            2

/* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_USER_BITS [01:00] */
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_USER_BITS_MASK           0x00000003
#define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_USER_BITS_SHIFT          0

/***************************************************************************
 *CX23_REC_TIME_CONFIG - Record Time Configuration Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */
#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_reserved_for_eco0_MASK  0xfe000000
#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25

/* XPT_RAVE :: CX23_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */
#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_COUNT_MODE_MASK     0x01000000
#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT    24

/* XPT_RAVE :: CX23_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */
#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK    0x00ffffff
#define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT   0

/***************************************************************************
 *CX23_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK    0xff000000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT   24

/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco0_MASK  0x00800000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23

/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK    0x007f0000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT   16

/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco1_MASK  0x00008000
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15

/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK    0x00007f00
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT   8

/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco2_MASK  0x000000fc
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2

/* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK   0x00000003
#define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT  0

/***************************************************************************
 *CX23_PIC_CTR - Picture Counter register
 ***************************************************************************/
/* XPT_RAVE :: CX23_PIC_CTR :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_CX23_PIC_CTR_reserved0_SHIFT                 16

/* XPT_RAVE :: CX23_PIC_CTR :: VALUE [15:00] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_VALUE_MASK                      0x0000ffff
#define BCHP_XPT_RAVE_CX23_PIC_CTR_VALUE_SHIFT                     0

/***************************************************************************
 *CX23_PIC_CTR_MODE - Picture Counter Mode Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_PIC_CTR_MODE :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved0_MASK             0x80000000
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved0_SHIFT            31

/* XPT_RAVE :: CX23_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK   0x70000000
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT  28

/* XPT_RAVE :: CX23_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_EN_MASK            0x08000000
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_EN_SHIFT           27

/* XPT_RAVE :: CX23_PIC_CTR_MODE :: reserved1 [26:26] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved1_MASK             0x04000000
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved1_SHIFT            26

/* XPT_RAVE :: CX23_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_MODE_MASK          0x03000000
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT         24

/* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV0 [23:16] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV0_MASK                  0x00ff0000
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV0_SHIFT                 16

/* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV1 [15:08] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV1_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV1_SHIFT                 8

/* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV2 [07:00] */
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV2_MASK                  0x000000ff
#define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV2_SHIFT                 0

/***************************************************************************
 *CX23_REC_TIMER - Record Timer Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_TIMER :: REC_TIMER [31:00] */
#define BCHP_XPT_RAVE_CX23_REC_TIMER_REC_TIMER_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX23_REC_TIMER_REC_TIMER_SHIFT               0

/***************************************************************************
 *CX23_REC_STATE0 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_STATE0 :: reserved_for_eco0 [31:18] */
#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco0_MASK       0xfffc0000
#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco0_SHIFT      18

/* XPT_RAVE :: CX23_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */
#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INIT_TIME_LO_MASK        0x0003ff00
#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INIT_TIME_LO_SHIFT       8

/* XPT_RAVE :: CX23_REC_STATE0 :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco1_MASK       0x000000f0
#define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco1_SHIFT      4

/* XPT_RAVE :: CX23_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */
#define BCHP_XPT_RAVE_CX23_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c
#define BCHP_XPT_RAVE_CX23_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2

/* XPT_RAVE :: CX23_REC_STATE0 :: TS_INITIALIZED [01:01] */
#define BCHP_XPT_RAVE_CX23_REC_STATE0_TS_INITIALIZED_MASK          0x00000002
#define BCHP_XPT_RAVE_CX23_REC_STATE0_TS_INITIALIZED_SHIFT         1

/* XPT_RAVE :: CX23_REC_STATE0 :: REC_INITIALIZED [00:00] */
#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INITIALIZED_MASK         0x00000001
#define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INITIALIZED_SHIFT        0

/***************************************************************************
 *CX23_REC_STATE1 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */
#define BCHP_XPT_RAVE_CX23_REC_STATE1_REC_INIT_TIME_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_CX23_REC_STATE1_REC_INIT_TIME_HI_SHIFT       0

/***************************************************************************
 *CX23_REC_STATE2 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_STATE2 :: INT_TIME_STAMP [31:00] */
#define BCHP_XPT_RAVE_CX23_REC_STATE2_INT_TIME_STAMP_MASK          0xffffffff
#define BCHP_XPT_RAVE_CX23_REC_STATE2_INT_TIME_STAMP_SHIFT         0

/***************************************************************************
 *CX23_REC_STATE2b - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */
#define BCHP_XPT_RAVE_CX23_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX23_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0

/***************************************************************************
 *CX23_REC_STATE3 - Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_STATE3 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_CX23_REC_STATE3_reserved_for_eco0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_CX23_REC_STATE3_reserved_for_eco0_SHIFT      9

/* XPT_RAVE :: CX23_REC_STATE3 :: REC_DSS_PARITY [08:08] */
#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_DSS_PARITY_MASK          0x00000100
#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_DSS_PARITY_SHIFT         8

/* XPT_RAVE :: CX23_REC_STATE3 :: REC_COUNT_HI [07:00] */
#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_COUNT_HI_MASK            0x000000ff
#define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_COUNT_HI_SHIFT           0

/***************************************************************************
 *CX23_REC_COUNT - Record Packet Count Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_COUNT :: REC_COUNT [31:00] */
#define BCHP_XPT_RAVE_CX23_REC_COUNT_REC_COUNT_MASK                0xffffffff
#define BCHP_XPT_RAVE_CX23_REC_COUNT_REC_COUNT_SHIFT               0

/***************************************************************************
 *CX23_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: reserved0 [31:18] */
#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_reserved0_MASK         0xfffc0000
#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_reserved0_SHIFT        18

/* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */
#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK      0x00030000
#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT     16

/* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */
#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK     0x0000ffff
#define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT    0

/***************************************************************************
 *CX23_REC_RESERVE_STATE1 - Reserved Record State Register
 ***************************************************************************/
/* XPT_RAVE :: CX23_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *CX23_RAVE_Reg_0 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX23_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_0_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_0_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX23_RAVE_Reg_1 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX23_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_1_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_1_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX23_RAVE_Reg_2 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX23_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_2_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_2_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *CX23_RAVE_Reg_3 - Reserved Rave Register for future use
 ***************************************************************************/
/* XPT_RAVE :: CX23_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_3_reserved_for_eco0_MASK       0xffffffff
#define BCHP_XPT_RAVE_CX23_RAVE_Reg_3_reserved_for_eco0_SHIFT      0

/***************************************************************************
 *SCD0_SCD_MISC_CONFIG - SCD 0 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD0_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD0_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD0_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD0_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD0_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD0_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD0_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD0_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD0_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD0_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD0_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD0_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD0_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD0_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD0_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD0_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD0_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_MISC_CONFIG - SCD 1 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD1_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD1_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD1_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD1_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD1_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD1_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD1_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD1_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD1_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD1_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD1_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD1_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD1_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD1_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD1_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD1_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD1_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_MISC_CONFIG - SCD 2 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD2_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD2_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD2_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD2_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD2_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD2_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD2_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD2_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD2_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD2_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD2_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD2_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD2_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD2_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD2_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD2_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD2_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_MISC_CONFIG - SCD 3 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD3_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD3_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD3_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD3_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD3_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD3_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD3_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD3_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD3_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD3_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD3_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD3_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD3_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD3_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD3_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD3_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD3_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_MISC_CONFIG - SCD 4 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD4_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD4_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD4_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD4_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD4_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD4_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD4_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD4_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD4_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD4_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD4_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD4_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD4_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD4_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD4_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD4_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD4_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_MISC_CONFIG - SCD 5 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD5_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD5_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD5_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD5_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD5_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD5_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD5_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD5_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD5_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD5_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD5_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD5_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD5_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD5_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD5_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD5_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD5_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_MISC_CONFIG - SCD 6 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD6_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD6_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD6_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD6_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD6_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD6_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD6_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD6_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD6_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD6_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD6_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD6_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD6_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD6_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD6_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD6_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD6_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_MISC_CONFIG - SCD 7 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD7_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD7_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD7_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD7_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD7_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD7_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD7_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD7_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD7_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD7_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD7_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD7_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD7_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD7_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD7_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD7_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD7_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_MISC_CONFIG - SCD 8 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD8_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD8_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD8_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD8_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD8_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD8_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD8_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD8_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD8_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD8_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD8_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD8_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD8_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD8_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD8_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD8_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD8_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_MISC_CONFIG - SCD 9 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_reserved_for_eco0_MASK  0xfffff800
#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD9_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK  0x000007ff
#define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD9_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD9_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD9_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3_reserved_for_eco0_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3_reserved_for_eco0_SHIFT  0

/***************************************************************************
 *SCD9_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK   0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT  0

/***************************************************************************
 *SCD9_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE0_COUNT_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_STATE0_COUNT_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD9_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE1_COUNT_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_STATE1_COUNT_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD9_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD9_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD9_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE3_MATCH_STACK1_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_STATE3_MATCH_STACK1_HI_SHIFT        0

/***************************************************************************
 *SCD9_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE4_MATCH_STACK0_HI_MASK         0xffffffff
#define BCHP_XPT_RAVE_SCD9_SCD_STATE4_MATCH_STACK0_HI_SHIFT        0

/***************************************************************************
 *SCD9_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK1_LO_MASK         0xffff0000
#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK1_LO_SHIFT        16

/* XPT_RAVE :: SCD9_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK0_LO_MASK         0x0000ffff
#define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK0_LO_SHIFT        0

/***************************************************************************
 *SCD9_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD9_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD9_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_MISC_CONFIG - SCD 10 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD10_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD10_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD10_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD10_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD10_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD10_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD10_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD10_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD10_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD10_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD10_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD10_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD10_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_MISC_CONFIG - SCD 11 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD11_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD11_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD11_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD11_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD11_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD11_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD11_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD11_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD11_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD11_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD11_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD11_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD11_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_MISC_CONFIG - SCD 12 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD12_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD12_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD12_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD12_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD12_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD12_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD12_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD12_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD12_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD12_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD12_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD12_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD12_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_MISC_CONFIG - SCD 13 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD13_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD13_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD13_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD13_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD13_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD13_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD13_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD13_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD13_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD13_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD13_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD13_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD13_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_MISC_CONFIG - SCD 14 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD14_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD14_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD14_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD14_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD14_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD14_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD14_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD14_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD14_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD14_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD14_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD14_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD14_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_MISC_CONFIG - SCD 15 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD15_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD15_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD15_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD15_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD15_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD15_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD15_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD15_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD15_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD15_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD15_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD15_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD15_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_MISC_CONFIG - SCD 16 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD16_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD16_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD16_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD16_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD16_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD16_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD16_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD16_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD16_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD16_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD16_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD16_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD16_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_MISC_CONFIG - SCD 17 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD17_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD17_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD17_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD17_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD17_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD17_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD17_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD17_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD17_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD17_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD17_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD17_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD17_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_MISC_CONFIG - SCD 18 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD18_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD18_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD18_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD18_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD18_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD18_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD18_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD18_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD18_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD18_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD18_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD18_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD18_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_MISC_CONFIG - SCD 19 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD19_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD19_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD19_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD19_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD19_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD19_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD19_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD19_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD19_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD19_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD19_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD19_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD19_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_MISC_CONFIG - SCD 20 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD20_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD20_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD20_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD20_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD20_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD20_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD20_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD20_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD20_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD20_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD20_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD20_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD20_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_MISC_CONFIG - SCD 21 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD21_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD21_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD21_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD21_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD21_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD21_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD21_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD21_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD21_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD21_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD21_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD21_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD21_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_MISC_CONFIG - SCD 22 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD22_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD22_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD22_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD22_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD22_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD22_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD22_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD22_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD22_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD22_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD22_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD22_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD22_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_MISC_CONFIG - SCD 23 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD23_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD23_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD23_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD23_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD23_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD23_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD23_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD23_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD23_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD23_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD23_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD23_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD23_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_MISC_CONFIG - SCD 24 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD24_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD24_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD24_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD24_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD24_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD24_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD24_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD24_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD24_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD24_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD24_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD24_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD24_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_MISC_CONFIG - SCD 25 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD25_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD25_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD25_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD25_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD25_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD25_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD25_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD25_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD25_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD25_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD25_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD25_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD25_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_MISC_CONFIG - SCD 26 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD26_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD26_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD26_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD26_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD26_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD26_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD26_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD26_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD26_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD26_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD26_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD26_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD26_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_MISC_CONFIG - SCD 27 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD27_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD27_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD27_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD27_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD27_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD27_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD27_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD27_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD27_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD27_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD27_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD27_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD27_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_MISC_CONFIG - SCD 28 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD28_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD28_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD28_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD28_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD28_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD28_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD28_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD28_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD28_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD28_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD28_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD28_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD28_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_MISC_CONFIG - SCD 29 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD29_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD29_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD29_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD29_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD29_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD29_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD29_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD29_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD29_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD29_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD29_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD29_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD29_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_MISC_CONFIG - SCD 30 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD30_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD30_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD30_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD30_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD30_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD30_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD30_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD30_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD30_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD30_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD30_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD30_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD30_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_MISC_CONFIG - SCD 31 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD31_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD31_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD31_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD31_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD31_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD31_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD31_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD31_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD31_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD31_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD31_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD31_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD31_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_MISC_CONFIG - SCD 32 Misc Config Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */
#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800
#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11

/* XPT_RAVE :: SCD32_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff
#define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE6 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE7 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE8 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE9 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE10 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_COMP_STATE11 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_RESERVE_COMP_STATE0 - Reserved Comparator State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_PES_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_PES_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_PES_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_PES_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3_reserved_for_eco0_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_PACKET_COUNT - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK  0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *SCD32_RESERVE_PES_STATE0 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_RESERVE_PES_STATE1 - Reserved PES State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_SCD_STATE0 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE0_COUNT_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_STATE0_COUNT_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD32_SCD_STATE1 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE1_COUNT_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_STATE1_COUNT_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD32_SCD_STATE2 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD32_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD32_SCD_STATE3 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE3_MATCH_STACK1_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_STATE3_MATCH_STACK1_HI_SHIFT       0

/***************************************************************************
 *SCD32_SCD_STATE4 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE4_MATCH_STACK0_HI_MASK        0xffffffff
#define BCHP_XPT_RAVE_SCD32_SCD_STATE4_MATCH_STACK0_HI_SHIFT       0

/***************************************************************************
 *SCD32_SCD_STATE5 - SCD State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK1_LO_MASK        0xffff0000
#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK1_LO_SHIFT       16

/* XPT_RAVE :: SCD32_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */
#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK0_LO_MASK        0x0000ffff
#define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK0_LO_SHIFT       0

/***************************************************************************
 *SCD32_RESERVED_STATE0 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_RESERVED_STATE1 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_RESERVED_STATE2 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *SCD32_RESERVED_STATE3 - SCD Reserved State Register
 ***************************************************************************/
/* XPT_RAVE :: SCD32_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff
#define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3_reserved_for_eco0_SHIFT 0

/***************************************************************************
 *XPU_CONFIG - XPU TEST ENABLE REGISTER
 ***************************************************************************/
/* XPT_RAVE :: XPU_CONFIG :: reserved0 [31:01] */
#define BCHP_XPT_RAVE_XPU_CONFIG_reserved0_MASK                    0xfffffffe
#define BCHP_XPT_RAVE_XPU_CONFIG_reserved0_SHIFT                   1

/* XPT_RAVE :: XPU_CONFIG :: TEST_ENABLE [00:00] */
#define BCHP_XPT_RAVE_XPU_CONFIG_TEST_ENABLE_MASK                  0x00000001
#define BCHP_XPT_RAVE_XPU_CONFIG_TEST_ENABLE_SHIFT                 0

/***************************************************************************
 *XPU_TEST_CONTROL - XPU TEST CONTROL REGISTER
 ***************************************************************************/
/* XPT_RAVE :: XPU_TEST_CONTROL :: reserved0 [31:04] */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_reserved0_MASK              0xfffffff0
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_reserved0_SHIFT             4

/* XPT_RAVE :: XPU_TEST_CONTROL :: EXT_IN [03:02] */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IN_MASK                 0x0000000c
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IN_SHIFT                2

/* XPT_RAVE :: XPU_TEST_CONTROL :: WAKE [01:01] */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_WAKE_MASK                   0x00000002
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_WAKE_SHIFT                  1

/* XPT_RAVE :: XPU_TEST_CONTROL :: INTR [00:00] */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_INTR_MASK                   0x00000001
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_INTR_SHIFT                  0

/***************************************************************************
 *XPU_TEST_CONTROL_EXT_IO - XPU TEST CONTROL EXT IO
 ***************************************************************************/
/* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: reserved0 [31:09] */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_reserved0_MASK       0xfffffe00
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_reserved0_SHIFT      9

/* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: WAIT [08:08] */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_WAIT_MASK            0x00000100
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_WAIT_SHIFT           8

/* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: RD_DATA [07:00] */
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_RD_DATA_MASK         0x000000ff
#define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_RD_DATA_SHIFT        0

/***************************************************************************
 *XPU_TEST_OBSERVE_0 - XPU TEST OBSERVE REGISTER
 ***************************************************************************/
/* XPT_RAVE :: XPU_TEST_OBSERVE_0 :: reserved0 [31:02] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_reserved0_MASK            0xfffffffc
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_reserved0_SHIFT           2

/* XPT_RAVE :: XPU_TEST_OBSERVE_0 :: P_BITS [01:00] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_P_BITS_MASK               0x00000003
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_P_BITS_SHIFT              0

/***************************************************************************
 *XPU_TEST_OBSERVE_1 - XPU TEST OBSERVE REGISTER
 ***************************************************************************/
/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: reserved0 [31:31] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_reserved0_MASK            0x80000000
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_reserved0_SHIFT           31

/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_PSW [30:20] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PSW_MASK            0x7ff00000
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PSW_SHIFT           20

/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_PC [19:08] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PC_MASK             0x000fff00
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PC_SHIFT            8

/* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_DATA [07:00] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_DATA_MASK           0x000000ff
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_DATA_SHIFT          0

/***************************************************************************
 *XPU_TEST_OBSERVE_EXT_IO - XPU TEST OBSERVE EXT IO REGISTER
 ***************************************************************************/
/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: reserved0 [31:22] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_reserved0_MASK       0xffc00000
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_reserved0_SHIFT      22

/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: ADDR [21:10] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_ADDR_MASK            0x003ffc00
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_ADDR_SHIFT           10

/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: WR_DATA [09:02] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_DATA_MASK         0x000003fc
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_DATA_SHIFT        2

/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: RD_STROBE [01:01] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_RD_STROBE_MASK       0x00000002
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_RD_STROBE_SHIFT      1

/* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: WR_STROBE [00:00] */
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_STROBE_MASK       0x00000001
#define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_STROBE_SHIFT      0

/***************************************************************************
 *RAVE_DIAGNOSTICS_CONTROL - RAVE Diagnostics Control Register
 ***************************************************************************/
/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: reserved0 [31:14] */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved0_MASK      0xffffc000
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved0_SHIFT     14

/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: UPPER_TESTBUS_SEL [13:09] */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_UPPER_TESTBUS_SEL_MASK 0x00003e00
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_UPPER_TESTBUS_SEL_SHIFT 9

/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: LOWER_TESTBUS_SEL [08:04] */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_LOWER_TESTBUS_SEL_MASK 0x000001f0
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_LOWER_TESTBUS_SEL_SHIFT 4

/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: reserved_for_eco1 [03:03] */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved_for_eco1_MASK 0x00000008
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved_for_eco1_SHIFT 3

/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: NEXT_BREAKPOINT [02:02] */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_NEXT_BREAKPOINT_MASK 0x00000004
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_NEXT_BREAKPOINT_SHIFT 2

/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: BREAKPOINT_EN [01:01] */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_BREAKPOINT_EN_MASK  0x00000002
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_BREAKPOINT_EN_SHIFT 1

/* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: DIAG_EN [00:00] */
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_DIAG_EN_MASK        0x00000001
#define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_DIAG_EN_SHIFT       0

/***************************************************************************
 *STOP_PACKET_COUNT_VALUE - Stop Packet Count Value
 ***************************************************************************/
/* XPT_RAVE :: STOP_PACKET_COUNT_VALUE :: STOP_PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE_STOP_PACKET_COUNT_MASK 0xffffffff
#define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE_STOP_PACKET_COUNT_SHIFT 0

/***************************************************************************
 *AVS_SCV_FILTER_MODE_CONTROL - AVS SCV Filter mode
 ***************************************************************************/
/* XPT_RAVE :: AVS_SCV_FILTER_MODE_CONTROL :: reserved0 [31:02] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_reserved0_MASK   0xfffffffc
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_reserved0_SHIFT  2

/* XPT_RAVE :: AVS_SCV_FILTER_MODE_CONTROL :: AVS_SCV_FILTER_MODE [01:00] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_AVS_SCV_FILTER_MODE_MASK 0x00000003
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_AVS_SCV_FILTER_MODE_SHIFT 0

/***************************************************************************
 *AVS_SCV_FILTER_VALUE_0_TO_3 - AVS SCV Filter value 0 to 3
 ***************************************************************************/
/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_3 [31:24] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_3_MASK   0xff000000
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_3_SHIFT  24

/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_2 [23:16] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_2_MASK   0x00ff0000
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_2_SHIFT  16

/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_1 [15:08] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_1_MASK   0x0000ff00
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_1_SHIFT  8

/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_0 [07:00] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_0_MASK   0x000000ff
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_0_SHIFT  0

/***************************************************************************
 *AVS_SCV_FILTER_VALUE_4_TO_7 - AVS SCV Filter value 4 to 7
 ***************************************************************************/
/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_7 [31:24] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_7_MASK   0xff000000
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_7_SHIFT  24

/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_6 [23:16] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_6_MASK   0x00ff0000
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_6_SHIFT  16

/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_5 [15:08] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_5_MASK   0x0000ff00
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_5_SHIFT  8

/* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_4 [07:00] */
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_4_MASK   0x000000ff
#define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_4_SHIFT  0

/***************************************************************************
 *AV_STATUS - RAVE Status
 ***************************************************************************/
/* XPT_RAVE :: AV_STATUS :: reserved0 [31:26] */
#define BCHP_XPT_RAVE_AV_STATUS_reserved0_MASK                     0xfc000000
#define BCHP_XPT_RAVE_AV_STATUS_reserved0_SHIFT                    26

/* XPT_RAVE :: AV_STATUS :: XPU_RDY [25:25] */
#define BCHP_XPT_RAVE_AV_STATUS_XPU_RDY_MASK                       0x02000000
#define BCHP_XPT_RAVE_AV_STATUS_XPU_RDY_SHIFT                      25

/* XPT_RAVE :: AV_STATUS :: ITB_MEM_STATE_IDLE [24:24] */
#define BCHP_XPT_RAVE_AV_STATUS_ITB_MEM_STATE_IDLE_MASK            0x01000000
#define BCHP_XPT_RAVE_AV_STATUS_ITB_MEM_STATE_IDLE_SHIFT           24

/* XPT_RAVE :: AV_STATUS :: CDB_MEM_STATE_IDLE [23:23] */
#define BCHP_XPT_RAVE_AV_STATUS_CDB_MEM_STATE_IDLE_MASK            0x00800000
#define BCHP_XPT_RAVE_AV_STATUS_CDB_MEM_STATE_IDLE_SHIFT           23

/* XPT_RAVE :: AV_STATUS :: HWA_PKT_ACTIVE [22:22] */
#define BCHP_XPT_RAVE_AV_STATUS_HWA_PKT_ACTIVE_MASK                0x00400000
#define BCHP_XPT_RAVE_AV_STATUS_HWA_PKT_ACTIVE_SHIFT               22

/* XPT_RAVE :: AV_STATUS :: DMA_BUSY [21:21] */
#define BCHP_XPT_RAVE_AV_STATUS_DMA_BUSY_MASK                      0x00200000
#define BCHP_XPT_RAVE_AV_STATUS_DMA_BUSY_SHIFT                     21

/* XPT_RAVE :: AV_STATUS :: AV_MUX_BUF_OVERFLOW [20:20] */
#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUF_OVERFLOW_MASK           0x00100000
#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUF_OVERFLOW_SHIFT          20

/* XPT_RAVE :: AV_STATUS :: AV_MUX_BUFFER_WATERMARK [19:10] */
#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_WATERMARK_MASK       0x000ffc00
#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_WATERMARK_SHIFT      10

/* XPT_RAVE :: AV_STATUS :: AV_MUX_BUFFER_DEPTH [09:00] */
#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_DEPTH_MASK           0x000003ff
#define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_DEPTH_SHIFT          0

/***************************************************************************
 *PACKET_COUNT - RAVE input packet counter
 ***************************************************************************/
/* XPT_RAVE :: PACKET_COUNT :: PACKET_COUNT [31:00] */
#define BCHP_XPT_RAVE_PACKET_COUNT_PACKET_COUNT_MASK               0xffffffff
#define BCHP_XPT_RAVE_PACKET_COUNT_PACKET_COUNT_SHIFT              0

/***************************************************************************
 *DATA_START_ADDR_A - Pkt and HWA data buffer A base addresses
 ***************************************************************************/
/* XPT_RAVE :: DATA_START_ADDR_A :: reserved0 [31:27] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved0_MASK             0xf8000000
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved0_SHIFT            27

/* XPT_RAVE :: DATA_START_ADDR_A :: HWA_START [26:16] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_HWA_START_MASK             0x07ff0000
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_HWA_START_SHIFT            16

/* XPT_RAVE :: DATA_START_ADDR_A :: reserved1 [15:11] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved1_MASK             0x0000f800
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved1_SHIFT            11

/* XPT_RAVE :: DATA_START_ADDR_A :: PKT_START [10:00] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_PKT_START_MASK             0x000007ff
#define BCHP_XPT_RAVE_DATA_START_ADDR_A_PKT_START_SHIFT            0

/***************************************************************************
 *DATA_START_ADDR_B - Pkt and HWA data buffer B base addresses
 ***************************************************************************/
/* XPT_RAVE :: DATA_START_ADDR_B :: reserved0 [31:27] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved0_MASK             0xf8000000
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved0_SHIFT            27

/* XPT_RAVE :: DATA_START_ADDR_B :: HWA_START [26:16] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_HWA_START_MASK             0x07ff0000
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_HWA_START_SHIFT            16

/* XPT_RAVE :: DATA_START_ADDR_B :: reserved1 [15:11] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved1_MASK             0x0000f800
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved1_SHIFT            11

/* XPT_RAVE :: DATA_START_ADDR_B :: PKT_START [10:00] */
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_PKT_START_MASK             0x000007ff
#define BCHP_XPT_RAVE_DATA_START_ADDR_B_PKT_START_SHIFT            0

/***************************************************************************
 *WATCHDOG_TIMER_VALUE - Watchdog Timer Timeout Value
 ***************************************************************************/
/* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: reserved0 [31:17] */
#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_reserved0_MASK          0xfffe0000
#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_reserved0_SHIFT         17

/* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: WATCHDOG_TIMER_ENABLE [16:16] */
#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_ENABLE_MASK 0x00010000
#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_ENABLE_SHIFT 16

/* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: WATCHDOG_TIMER_LOAD_VALUE [15:00] */
#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_LOAD_VALUE_MASK 0x0000ffff
#define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_LOAD_VALUE_SHIFT 0

/***************************************************************************
 *MISC_CONTROL - Miscellaneous Control
 ***************************************************************************/
/* XPT_RAVE :: MISC_CONTROL :: PACKET_CNT_CLR [31:31] */
#define BCHP_XPT_RAVE_MISC_CONTROL_PACKET_CNT_CLR_MASK             0x80000000
#define BCHP_XPT_RAVE_MISC_CONTROL_PACKET_CNT_CLR_SHIFT            31

/* XPT_RAVE :: MISC_CONTROL :: WMARK_GRANULARITY [30:28] */
#define BCHP_XPT_RAVE_MISC_CONTROL_WMARK_GRANULARITY_MASK          0x70000000
#define BCHP_XPT_RAVE_MISC_CONTROL_WMARK_GRANULARITY_SHIFT         28

/* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco0 [27:26] */
#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco0_MASK          0x0c000000
#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco0_SHIFT         26

/* XPT_RAVE :: MISC_CONTROL :: NUM_CONTEXTS [25:20] */
#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_CONTEXTS_MASK               0x03f00000
#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_CONTEXTS_SHIFT              20

/* XPT_RAVE :: MISC_CONTROL :: EMU_STATE_CLEAR [19:19] */
#define BCHP_XPT_RAVE_MISC_CONTROL_EMU_STATE_CLEAR_MASK            0x00080000
#define BCHP_XPT_RAVE_MISC_CONTROL_EMU_STATE_CLEAR_SHIFT           19

/* XPT_RAVE :: MISC_CONTROL :: AV_WMARK_CLEAR [18:18] */
#define BCHP_XPT_RAVE_MISC_CONTROL_AV_WMARK_CLEAR_MASK             0x00040000
#define BCHP_XPT_RAVE_MISC_CONTROL_AV_WMARK_CLEAR_SHIFT            18

/* XPT_RAVE :: MISC_CONTROL :: DMA_SPEEDUP_EN [17:17] */
#define BCHP_XPT_RAVE_MISC_CONTROL_DMA_SPEEDUP_EN_MASK             0x00020000
#define BCHP_XPT_RAVE_MISC_CONTROL_DMA_SPEEDUP_EN_SHIFT            17

/* XPT_RAVE :: MISC_CONTROL :: MUX_BUFFER_SLOT_SIZE [16:16] */
#define BCHP_XPT_RAVE_MISC_CONTROL_MUX_BUFFER_SLOT_SIZE_MASK       0x00010000
#define BCHP_XPT_RAVE_MISC_CONTROL_MUX_BUFFER_SLOT_SIZE_SHIFT      16

/* XPT_RAVE :: MISC_CONTROL :: INPUT_READ_RATE [15:12] */
#define BCHP_XPT_RAVE_MISC_CONTROL_INPUT_READ_RATE_MASK            0x0000f000
#define BCHP_XPT_RAVE_MISC_CONTROL_INPUT_READ_RATE_SHIFT           12

/* XPT_RAVE :: MISC_CONTROL :: PES_COMPARATOR_RESET [11:11] */
#define BCHP_XPT_RAVE_MISC_CONTROL_PES_COMPARATOR_RESET_MASK       0x00000800
#define BCHP_XPT_RAVE_MISC_CONTROL_PES_COMPARATOR_RESET_SHIFT      11

/* XPT_RAVE :: MISC_CONTROL :: FORCE_SWITCH [10:10] */
#define BCHP_XPT_RAVE_MISC_CONTROL_FORCE_SWITCH_MASK               0x00000400
#define BCHP_XPT_RAVE_MISC_CONTROL_FORCE_SWITCH_SHIFT              10

/* XPT_RAVE :: MISC_CONTROL :: HW_FORCE_SWITCH_EN [09:09] */
#define BCHP_XPT_RAVE_MISC_CONTROL_HW_FORCE_SWITCH_EN_MASK         0x00000200
#define BCHP_XPT_RAVE_MISC_CONTROL_HW_FORCE_SWITCH_EN_SHIFT        9

/* XPT_RAVE :: MISC_CONTROL :: COUNTER_MODE [08:08] */
#define BCHP_XPT_RAVE_MISC_CONTROL_COUNTER_MODE_MASK               0x00000100
#define BCHP_XPT_RAVE_MISC_CONTROL_COUNTER_MODE_SHIFT              8

/* XPT_RAVE :: MISC_CONTROL :: NUM_DMA_CYCLES [07:04] */
#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_DMA_CYCLES_MASK             0x000000f0
#define BCHP_XPT_RAVE_MISC_CONTROL_NUM_DMA_CYCLES_SHIFT            4

/* XPT_RAVE :: MISC_CONTROL :: AV_ENABLE [03:03] */
#define BCHP_XPT_RAVE_MISC_CONTROL_AV_ENABLE_MASK                  0x00000008
#define BCHP_XPT_RAVE_MISC_CONTROL_AV_ENABLE_SHIFT                 3

/* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco1 [02:02] */
#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco1_MASK          0x00000004
#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco1_SHIFT         2

/* XPT_RAVE :: MISC_CONTROL :: PS_WAKE [01:01] */
#define BCHP_XPT_RAVE_MISC_CONTROL_PS_WAKE_MASK                    0x00000002
#define BCHP_XPT_RAVE_MISC_CONTROL_PS_WAKE_SHIFT                   1

/* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco2 [00:00] */
#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco2_MASK          0x00000001
#define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco2_SHIFT         0

/***************************************************************************
 *BASE_ADDRESSES - Record and SCD Base Addresses
 ***************************************************************************/
/* XPT_RAVE :: BASE_ADDRESSES :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_BASE_ADDRESSES_reserved0_MASK                0xfffff000
#define BCHP_XPT_RAVE_BASE_ADDRESSES_reserved0_SHIFT               12

/* XPT_RAVE :: BASE_ADDRESSES :: SCD_BASE_ADDR [11:00] */
#define BCHP_XPT_RAVE_BASE_ADDRESSES_SCD_BASE_ADDR_MASK            0x00000fff
#define BCHP_XPT_RAVE_BASE_ADDRESSES_SCD_BASE_ADDR_SHIFT           0

/***************************************************************************
 *CX_HOLD_CLR_STATUS - Context Hold Status and Clear
 ***************************************************************************/
/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: reserved0 [31:24] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_reserved0_MASK            0xff000000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_reserved0_SHIFT           24

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX23_HOLD [23:23] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX23_HOLD_MASK            0x00800000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX23_HOLD_SHIFT           23

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX22_HOLD [22:22] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX22_HOLD_MASK            0x00400000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX22_HOLD_SHIFT           22

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX21_HOLD [21:21] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX21_HOLD_MASK            0x00200000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX21_HOLD_SHIFT           21

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX20_HOLD [20:20] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX20_HOLD_MASK            0x00100000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX20_HOLD_SHIFT           20

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX19_HOLD [19:19] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX19_HOLD_MASK            0x00080000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX19_HOLD_SHIFT           19

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX18_HOLD [18:18] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX18_HOLD_MASK            0x00040000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX18_HOLD_SHIFT           18

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX17_HOLD [17:17] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX17_HOLD_MASK            0x00020000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX17_HOLD_SHIFT           17

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX16_HOLD [16:16] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX16_HOLD_MASK            0x00010000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX16_HOLD_SHIFT           16

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX15_HOLD [15:15] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX15_HOLD_MASK            0x00008000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX15_HOLD_SHIFT           15

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX14_HOLD [14:14] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX14_HOLD_MASK            0x00004000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX14_HOLD_SHIFT           14

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX13_HOLD [13:13] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX13_HOLD_MASK            0x00002000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX13_HOLD_SHIFT           13

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX12_HOLD [12:12] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX12_HOLD_MASK            0x00001000
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX12_HOLD_SHIFT           12

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX11_HOLD [11:11] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX11_HOLD_MASK            0x00000800
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX11_HOLD_SHIFT           11

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX10_HOLD [10:10] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX10_HOLD_MASK            0x00000400
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX10_HOLD_SHIFT           10

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX9_HOLD [09:09] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX9_HOLD_MASK             0x00000200
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX9_HOLD_SHIFT            9

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX8_HOLD [08:08] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX8_HOLD_MASK             0x00000100
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX8_HOLD_SHIFT            8

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX7_HOLD [07:07] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX7_HOLD_MASK             0x00000080
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX7_HOLD_SHIFT            7

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX6_HOLD [06:06] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX6_HOLD_MASK             0x00000040
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX6_HOLD_SHIFT            6

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX5_HOLD [05:05] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX5_HOLD_MASK             0x00000020
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX5_HOLD_SHIFT            5

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX4_HOLD [04:04] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX4_HOLD_MASK             0x00000010
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX4_HOLD_SHIFT            4

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX3_HOLD [03:03] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX3_HOLD_MASK             0x00000008
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX3_HOLD_SHIFT            3

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX2_HOLD [02:02] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX2_HOLD_MASK             0x00000004
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX2_HOLD_SHIFT            2

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX1_HOLD [01:01] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX1_HOLD_MASK             0x00000002
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX1_HOLD_SHIFT            1

/* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX0_HOLD [00:00] */
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX0_HOLD_MASK             0x00000001
#define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX0_HOLD_SHIFT            0

/***************************************************************************
 *BAND_HOLD_CLR_STATUS - Band Hold Status and Clear
 ***************************************************************************/
/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: reserved0 [31:17] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved0_MASK          0xfffe0000
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved0_SHIFT         17

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK4_HOLD [16:16] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK4_HOLD_MASK     0x00010000
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK4_HOLD_SHIFT    16

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK3_HOLD [15:15] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK3_HOLD_MASK     0x00008000
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK3_HOLD_SHIFT    15

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK2_HOLD [14:14] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK2_HOLD_MASK     0x00004000
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK2_HOLD_SHIFT    14

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK1_HOLD [13:13] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK1_HOLD_MASK     0x00002000
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK1_HOLD_SHIFT    13

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK0_HOLD [12:12] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK0_HOLD_MASK     0x00001000
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK0_HOLD_SHIFT    12

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: reserved1 [11:07] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved1_MASK          0x00000f80
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved1_SHIFT         7

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND6_HOLD [06:06] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND6_HOLD_MASK  0x00000040
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND6_HOLD_SHIFT 6

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND5_HOLD [05:05] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND5_HOLD_MASK  0x00000020
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND5_HOLD_SHIFT 5

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND4_HOLD [04:04] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND4_HOLD_MASK  0x00000010
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND4_HOLD_SHIFT 4

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND3_HOLD [03:03] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND3_HOLD_MASK  0x00000008
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND3_HOLD_SHIFT 3

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND2_HOLD [02:02] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND2_HOLD_MASK  0x00000004
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND2_HOLD_SHIFT 2

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND1_HOLD [01:01] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND1_HOLD_MASK  0x00000002
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND1_HOLD_SHIFT 1

/* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND0_HOLD [00:00] */
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND0_HOLD_MASK  0x00000001
#define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND0_HOLD_SHIFT 0

/***************************************************************************
 *FW_WATERMARK - Firmware throughput watermark
 ***************************************************************************/
/* XPT_RAVE :: FW_WATERMARK :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_FW_WATERMARK_reserved0_MASK                  0xffff0000
#define BCHP_XPT_RAVE_FW_WATERMARK_reserved0_SHIFT                 16

/* XPT_RAVE :: FW_WATERMARK :: FIRMWARE_WMARK [15:00] */
#define BCHP_XPT_RAVE_FW_WATERMARK_FIRMWARE_WMARK_MASK             0x0000ffff
#define BCHP_XPT_RAVE_FW_WATERMARK_FIRMWARE_WMARK_SHIFT            0

/***************************************************************************
 *HW_WATCHDOG - Hardware Watchdog Counter
 ***************************************************************************/
/* XPT_RAVE :: HW_WATCHDOG :: reserved0 [31:16] */
#define BCHP_XPT_RAVE_HW_WATCHDOG_reserved0_MASK                   0xffff0000
#define BCHP_XPT_RAVE_HW_WATCHDOG_reserved0_SHIFT                  16

/* XPT_RAVE :: HW_WATCHDOG :: HW_WATCHDOG_COUNT [15:00] */
#define BCHP_XPT_RAVE_HW_WATCHDOG_HW_WATCHDOG_COUNT_MASK           0x0000ffff
#define BCHP_XPT_RAVE_HW_WATCHDOG_HW_WATCHDOG_COUNT_SHIFT          0

/***************************************************************************
 *MISC_CONTROL2 - Miscellaneous Control 2
 ***************************************************************************/
/* XPT_RAVE :: MISC_CONTROL2 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_reserved0_MASK                 0xffffff00
#define BCHP_XPT_RAVE_MISC_CONTROL2_reserved0_SHIFT                8

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN7 [07:07] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN7_MASK              0x00000080
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN7_SHIFT             7

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN6 [06:06] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN6_MASK              0x00000040
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN6_SHIFT             6

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN5 [05:05] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN5_MASK              0x00000020
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN5_SHIFT             5

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN4 [04:04] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN4_MASK              0x00000010
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN4_SHIFT             4

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN3 [03:03] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN3_MASK              0x00000008
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN3_SHIFT             3

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN2 [02:02] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN2_MASK              0x00000004
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN2_SHIFT             2

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN1 [01:01] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN1_MASK              0x00000002
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN1_SHIFT             1

/* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN0 [00:00] */
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN0_MASK              0x00000001
#define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN0_SHIFT             0

/***************************************************************************
 *RC0_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC0_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC0_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC0_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC0_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC0_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC1_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC1_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC1_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC1_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC1_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC1_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC2_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC2_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC2_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC2_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC2_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC2_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC3_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC3_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC3_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC3_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC3_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC3_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC4_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC4_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC4_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC4_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC4_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC4_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC5_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC5_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC5_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC5_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC5_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC5_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC6_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC6_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC6_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC6_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC6_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC6_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC7_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC7_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC7_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC7_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC7_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC7_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *RC8_SP_CONTROL - Seamless Pause Control
 ***************************************************************************/
/* XPT_RAVE :: RC8_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK        0x80000000
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT       31

/* XPT_RAVE :: RC8_SP_CONTROL :: reserved0 [30:30] */
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_reserved0_MASK                0x40000000
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_reserved0_SHIFT               30

/* XPT_RAVE :: RC8_SP_CONTROL :: REC_CX_NUM [29:24] */
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_REC_CX_NUM_MASK               0x3f000000
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_REC_CX_NUM_SHIFT              24

/* XPT_RAVE :: RC8_SP_CONTROL :: CXX_MASK [23:00] */
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_CXX_MASK_MASK                 0x00ffffff
#define BCHP_XPT_RAVE_RC8_SP_CONTROL_CXX_MASK_SHIFT                0

/***************************************************************************
 *AV_STATUS2 - RAVE Status
 ***************************************************************************/
/* XPT_RAVE :: AV_STATUS2 :: reserved0 [31:20] */
#define BCHP_XPT_RAVE_AV_STATUS2_reserved0_MASK                    0xfff00000
#define BCHP_XPT_RAVE_AV_STATUS2_reserved0_SHIFT                   20

/* XPT_RAVE :: AV_STATUS2 :: PONG_SCD_NUM [19:14] */
#define BCHP_XPT_RAVE_AV_STATUS2_PONG_SCD_NUM_MASK                 0x000fc000
#define BCHP_XPT_RAVE_AV_STATUS2_PONG_SCD_NUM_SHIFT                14

/* XPT_RAVE :: AV_STATUS2 :: PING_SCD_NUM [13:08] */
#define BCHP_XPT_RAVE_AV_STATUS2_PING_SCD_NUM_MASK                 0x00003f00
#define BCHP_XPT_RAVE_AV_STATUS2_PING_SCD_NUM_SHIFT                8

/* XPT_RAVE :: AV_STATUS2 :: PONG_CONTEXT_NUM [07:04] */
#define BCHP_XPT_RAVE_AV_STATUS2_PONG_CONTEXT_NUM_MASK             0x000000f0
#define BCHP_XPT_RAVE_AV_STATUS2_PONG_CONTEXT_NUM_SHIFT            4

/* XPT_RAVE :: AV_STATUS2 :: PING_CONTEXT_NUM [03:00] */
#define BCHP_XPT_RAVE_AV_STATUS2_PING_CONTEXT_NUM_MASK             0x0000000f
#define BCHP_XPT_RAVE_AV_STATUS2_PING_CONTEXT_NUM_SHIFT            0

/***************************************************************************
 *TM_DMEM - TM Control
 ***************************************************************************/
/* XPT_RAVE :: TM_DMEM :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TM_DMEM_reserved0_MASK                       0xffffff00
#define BCHP_XPT_RAVE_TM_DMEM_reserved0_SHIFT                      8

/* XPT_RAVE :: TM_DMEM :: TMB [07:04] */
#define BCHP_XPT_RAVE_TM_DMEM_TMB_MASK                             0x000000f0
#define BCHP_XPT_RAVE_TM_DMEM_TMB_SHIFT                            4

/* XPT_RAVE :: TM_DMEM :: TMA [03:00] */
#define BCHP_XPT_RAVE_TM_DMEM_TMA_MASK                             0x0000000f
#define BCHP_XPT_RAVE_TM_DMEM_TMA_SHIFT                            0

/***************************************************************************
 *TM_IMEM - TM Control
 ***************************************************************************/
/* XPT_RAVE :: TM_IMEM :: reserved0 [31:04] */
#define BCHP_XPT_RAVE_TM_IMEM_reserved0_MASK                       0xfffffff0
#define BCHP_XPT_RAVE_TM_IMEM_reserved0_SHIFT                      4

/* XPT_RAVE :: TM_IMEM :: TM [03:00] */
#define BCHP_XPT_RAVE_TM_IMEM_TM_MASK                              0x0000000f
#define BCHP_XPT_RAVE_TM_IMEM_TM_SHIFT                             0

/***************************************************************************
 *TM_POINTER_RAM - TM Control
 ***************************************************************************/
/* XPT_RAVE :: TM_POINTER_RAM :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TM_POINTER_RAM_reserved0_MASK                0xffffff00
#define BCHP_XPT_RAVE_TM_POINTER_RAM_reserved0_SHIFT               8

/* XPT_RAVE :: TM_POINTER_RAM :: TM [07:00] */
#define BCHP_XPT_RAVE_TM_POINTER_RAM_TM_MASK                       0x000000ff
#define BCHP_XPT_RAVE_TM_POINTER_RAM_TM_SHIFT                      0

/***************************************************************************
 *TM_MUX_BUFFER - TM Control
 ***************************************************************************/
/* XPT_RAVE :: TM_MUX_BUFFER :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TM_MUX_BUFFER_reserved0_MASK                 0xffffff00
#define BCHP_XPT_RAVE_TM_MUX_BUFFER_reserved0_SHIFT                8

/* XPT_RAVE :: TM_MUX_BUFFER :: TM [07:00] */
#define BCHP_XPT_RAVE_TM_MUX_BUFFER_TM_MASK                        0x000000ff
#define BCHP_XPT_RAVE_TM_MUX_BUFFER_TM_SHIFT                       0

/***************************************************************************
 *TM_CX_TABLE - TM Control
 ***************************************************************************/
/* XPT_RAVE :: TM_CX_TABLE :: reserved0 [31:04] */
#define BCHP_XPT_RAVE_TM_CX_TABLE_reserved0_MASK                   0xfffffff0
#define BCHP_XPT_RAVE_TM_CX_TABLE_reserved0_SHIFT                  4

/* XPT_RAVE :: TM_CX_TABLE :: TM [03:00] */
#define BCHP_XPT_RAVE_TM_CX_TABLE_TM_MASK                          0x0000000f
#define BCHP_XPT_RAVE_TM_CX_TABLE_TM_SHIFT                         0

/***************************************************************************
 *TM_CX_TABLE_HI - TM Control
 ***************************************************************************/
/* XPT_RAVE :: TM_CX_TABLE_HI :: reserved0 [31:04] */
#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_reserved0_MASK                0xfffffff0
#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_reserved0_SHIFT               4

/* XPT_RAVE :: TM_CX_TABLE_HI :: TM [03:00] */
#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_TM_MASK                       0x0000000f
#define BCHP_XPT_RAVE_TM_CX_TABLE_HI_TM_SHIFT                      0

/***************************************************************************
 *TM_SMEM - TM Control
 ***************************************************************************/
/* XPT_RAVE :: TM_SMEM :: reserved0 [31:04] */
#define BCHP_XPT_RAVE_TM_SMEM_reserved0_MASK                       0xfffffff0
#define BCHP_XPT_RAVE_TM_SMEM_reserved0_SHIFT                      4

/* XPT_RAVE :: TM_SMEM :: TM [03:00] */
#define BCHP_XPT_RAVE_TM_SMEM_TM_MASK                              0x0000000f
#define BCHP_XPT_RAVE_TM_SMEM_TM_SHIFT                             0

/***************************************************************************
 *INT_CX0 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX0 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX0_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX0_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX0 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX0_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX0_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX0 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX0_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX0_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX0 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX0_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX0_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX0 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX0_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX0_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX0 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX0_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX0_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX0 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX0_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX0_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX0 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX0_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX0_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX0 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX0_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX0_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX0 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX0_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX0_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX0 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX0_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX0_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX0 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX0_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX0_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX0 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX0_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX0_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX0 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX0_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX0_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX1 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX1 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX1_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX1_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX1 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX1_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX1_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX1 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX1_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX1_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX1 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX1_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX1_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX1 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX1_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX1_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX1 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX1_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX1_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX1 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX1_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX1_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX1 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX1_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX1_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX1 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX1_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX1_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX1 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX1_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX1_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX1 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX1_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX1_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX1 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX1_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX1_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX1 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX1_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX1_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX1 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX1_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX1_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX2 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX2 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX2_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX2_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX2 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX2_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX2_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX2 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX2_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX2_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX2 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX2_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX2_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX2 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX2_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX2_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX2 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX2_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX2_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX2 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX2_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX2_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX2 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX2_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX2_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX2 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX2_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX2_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX2 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX2_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX2_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX2 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX2_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX2_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX2 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX2_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX2_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX2 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX2_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX2_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX2 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX2_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX2_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX3 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX3 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX3_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX3_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX3 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX3_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX3_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX3 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX3_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX3_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX3 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX3_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX3_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX3 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX3_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX3_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX3 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX3_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX3_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX3 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX3_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX3_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX3 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX3_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX3_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX3 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX3_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX3_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX3 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX3_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX3_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX3 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX3_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX3_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX3 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX3_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX3_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX3 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX3_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX3_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX3 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX3_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX3_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX4 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX4 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX4_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX4_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX4 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX4_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX4_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX4 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX4_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX4_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX4 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX4_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX4_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX4 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX4_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX4_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX4 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX4_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX4_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX4 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX4_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX4_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX4 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX4_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX4_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX4 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX4_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX4_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX4 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX4_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX4_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX4 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX4_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX4_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX4 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX4_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX4_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX4 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX4_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX4_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX4 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX4_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX4_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX5 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX5 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX5_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX5_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX5 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX5 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX5 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX5 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX5 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX5 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX5 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX5 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX5 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX5 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX5 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX5 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX5 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX6 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX6 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX6_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX6_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX6 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX6_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX6_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX6 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX6_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX6_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX6 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX6_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX6_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX6 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX6_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX6_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX6 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX6_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX6_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX6 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX6_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX6_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX6 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX6_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX6_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX6 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX6_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX6_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX6 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX6_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX6_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX6 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX6_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX6_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX6 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX6_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX6_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX6 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX6_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX6_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX6 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX6_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX6_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX7 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX7 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX7_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX7_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX7 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX7_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX7_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX7 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX7_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX7_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX7 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX7_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX7_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX7 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX7_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX7_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX7 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX7_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX7_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX7 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX7_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX7_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX7 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX7_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX7_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX7 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX7_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX7_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX7 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX7_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX7_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX7 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX7_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX7_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX7 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX7_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX7_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX7 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX7_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX7_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX7 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX7_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX7_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX8 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX8 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX8_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX8_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX8 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX8_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX8_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX8 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX8_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX8_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX8 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX8_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX8_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX8 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX8_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX8_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX8 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX8_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX8_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX8 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX8_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX8_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX8 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX8_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX8_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX8 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX8_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX8_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX8 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX8_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX8_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX8 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX8_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX8_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX8 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX8_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX8_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX8 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX8_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX8_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX8 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX8_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX8_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX9 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX9 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX9_reserved0_MASK                       0xffff8000
#define BCHP_XPT_RAVE_INT_CX9_reserved0_SHIFT                      15

/* XPT_RAVE :: INT_CX9 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX9_SCD_INDEX_MASK                       0x00007000
#define BCHP_XPT_RAVE_INT_CX9_SCD_INDEX_SHIFT                      12

/* XPT_RAVE :: INT_CX9 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX9_ITB_UPPER_THRESH_INT_MASK            0x00000800
#define BCHP_XPT_RAVE_INT_CX9_ITB_UPPER_THRESH_INT_SHIFT           11

/* XPT_RAVE :: INT_CX9 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX9_ITB_LOWER_THRESH_INT_MASK            0x00000400
#define BCHP_XPT_RAVE_INT_CX9_ITB_LOWER_THRESH_INT_SHIFT           10

/* XPT_RAVE :: INT_CX9 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX9_CDB_UPPER_THRESH_INT_MASK            0x00000200
#define BCHP_XPT_RAVE_INT_CX9_CDB_UPPER_THRESH_INT_SHIFT           9

/* XPT_RAVE :: INT_CX9 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX9_CDB_LOWER_THRESH_INT_MASK            0x00000100
#define BCHP_XPT_RAVE_INT_CX9_CDB_LOWER_THRESH_INT_SHIFT           8

/* XPT_RAVE :: INT_CX9 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX9_LAST_CMD_INT_MASK                    0x00000080
#define BCHP_XPT_RAVE_INT_CX9_LAST_CMD_INT_SHIFT                   7

/* XPT_RAVE :: INT_CX9 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX9_SPLICE_INT_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_CX9_SPLICE_INT_SHIFT                     6

/* XPT_RAVE :: INT_CX9 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX9_ITB_OVERFLOW_INT_MASK                0x00000020
#define BCHP_XPT_RAVE_INT_CX9_ITB_OVERFLOW_INT_SHIFT               5

/* XPT_RAVE :: INT_CX9 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX9_CDB_OVERFLOW_INT_MASK                0x00000010
#define BCHP_XPT_RAVE_INT_CX9_CDB_OVERFLOW_INT_SHIFT               4

/* XPT_RAVE :: INT_CX9 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX9_CC_ERROR_INT_MASK                    0x00000008
#define BCHP_XPT_RAVE_INT_CX9_CC_ERROR_INT_SHIFT                   3

/* XPT_RAVE :: INT_CX9 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX9_TEI_ERROR_INT_MASK                   0x00000004
#define BCHP_XPT_RAVE_INT_CX9_TEI_ERROR_INT_SHIFT                  2

/* XPT_RAVE :: INT_CX9 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX9_PUSI_ERROR_INT_MASK                  0x00000002
#define BCHP_XPT_RAVE_INT_CX9_PUSI_ERROR_INT_SHIFT                 1

/* XPT_RAVE :: INT_CX9 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX9_EMU_ERROR_INT_MASK                   0x00000001
#define BCHP_XPT_RAVE_INT_CX9_EMU_ERROR_INT_SHIFT                  0

/***************************************************************************
 *INT_CX10 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX10 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX10_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX10_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX10 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX10_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX10_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX10 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX10_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX10_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX10 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX10_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX10_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX10 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX10_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX10_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX10 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX10_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX10_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX10 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX10_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX10_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX10 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX10_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX10_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX10 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX10_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX10_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX10 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX10_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX10_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX10 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX10_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX10_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX10 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX10_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX10_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX10 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX10_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX10_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX10 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX10_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX10_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX11 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX11 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX11_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX11_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX11 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX11_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX11_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX11 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX11_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX11_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX11 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX11_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX11_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX11 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX11_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX11_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX11 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX11_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX11_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX11 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX11_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX11_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX11 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX11_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX11_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX11 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX11_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX11_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX11 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX11_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX11_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX11 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX11_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX11_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX11 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX11_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX11_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX11 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX11_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX11_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX11 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX11_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX11_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX12 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX12 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX12_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX12_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX12 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX12_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX12_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX12 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX12_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX12_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX12 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX12_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX12_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX12 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX12_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX12_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX12 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX12_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX12_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX12 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX12_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX12_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX12 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX12_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX12_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX12 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX12_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX12_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX12 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX12_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX12_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX12 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX12_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX12_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX12 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX12_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX12_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX12 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX12_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX12_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX12 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX12_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX12_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX13 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX13 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX13_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX13_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX13 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX13_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX13_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX13 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX13_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX13_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX13 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX13_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX13_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX13 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX13_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX13_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX13 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX13_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX13_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX13 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX13_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX13_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX13 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX13_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX13_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX13 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX13_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX13_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX13 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX13_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX13_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX13 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX13_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX13_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX13 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX13_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX13_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX13 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX13_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX13_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX13 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX13_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX13_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX14 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX14 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX14_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX14_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX14 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX14_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX14_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX14 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX14_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX14_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX14 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX14_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX14_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX14 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX14_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX14_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX14 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX14_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX14_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX14 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX14_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX14_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX14 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX14_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX14_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX14 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX14_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX14_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX14 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX14_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX14_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX14 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX14_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX14_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX14 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX14_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX14_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX14 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX14_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX14_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX14 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX14_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX14_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX15 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX15 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX15_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX15_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX15 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX15_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX15_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX15 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX15_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX15_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX15 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX15_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX15_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX15 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX15_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX15_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX15 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX15_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX15_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX15 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX15_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX15_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX15 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX15_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX15_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX15 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX15_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX15_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX15 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX15_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX15_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX15 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX15_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX15_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX15 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX15_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX15_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX15 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX15_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX15_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX15 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX15_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX15_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX16 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX16 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX16_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX16_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX16 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX16_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX16_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX16 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX16_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX16_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX16 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX16_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX16_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX16 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX16_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX16_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX16 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX16_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX16_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX16 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX16_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX16_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX16 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX16_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX16_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX16 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX16_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX16_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX16 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX16_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX16_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX16 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX16_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX16_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX16 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX16_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX16_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX16 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX16_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX16_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX16 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX16_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX16_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX17 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX17 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX17_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX17_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX17 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX17_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX17_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX17 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX17_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX17_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX17 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX17_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX17_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX17 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX17_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX17_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX17 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX17_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX17_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX17 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX17_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX17_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX17 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX17_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX17_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX17 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX17_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX17_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX17 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX17_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX17_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX17 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX17_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX17_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX17 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX17_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX17_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX17 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX17_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX17_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX17 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX17_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX17_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX18 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX18 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX18_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX18_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX18 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX18_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX18_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX18 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX18_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX18_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX18 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX18_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX18_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX18 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX18_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX18_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX18 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX18_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX18_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX18 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX18_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX18_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX18 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX18_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX18_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX18 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX18_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX18_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX18 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX18_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX18_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX18 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX18_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX18_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX18 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX18_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX18_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX18 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX18_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX18_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX18 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX18_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX18_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX19 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX19 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX19_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX19_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX19 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX19_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX19_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX19 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX19_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX19_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX19 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX19_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX19_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX19 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX19_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX19_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX19 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX19_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX19_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX19 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX19_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX19_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX19 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX19_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX19_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX19 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX19_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX19_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX19 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX19_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX19_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX19 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX19_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX19_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX19 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX19_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX19_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX19 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX19_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX19_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX19 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX19_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX19_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX20 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX20 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX20_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX20_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX20 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX20_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX20_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX20 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX20_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX20_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX20 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX20_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX20_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX20 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX20_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX20_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX20 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX20_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX20_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX20 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX20_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX20_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX20 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX20_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX20_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX20 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX20_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX20_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX20 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX20_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX20_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX20 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX20_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX20_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX20 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX20_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX20_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX20 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX20_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX20_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX20 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX20_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX20_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX21 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX21 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX21_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX21_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX21 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX21_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX21_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX21 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX21_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX21_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX21 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX21_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX21_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX21 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX21_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX21_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX21 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX21_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX21_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX21 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX21_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX21_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX21 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX21_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX21_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX21 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX21_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX21_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX21 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX21_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX21_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX21 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX21_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX21_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX21 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX21_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX21_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX21 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX21_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX21_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX21 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX21_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX21_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX22 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX22 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX22_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX22_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX22 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX22_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX22_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX22 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX22_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX22_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX22 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX22_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX22_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX22 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX22_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX22_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX22 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX22_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX22_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX22 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX22_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX22_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX22 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX22_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX22_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX22 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX22_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX22_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX22 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX22_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX22_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX22 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX22_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX22_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX22 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX22_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX22_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX22 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX22_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX22_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX22 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX22_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX22_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_CX23 - Context Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_CX23 :: reserved0 [31:15] */
#define BCHP_XPT_RAVE_INT_CX23_reserved0_MASK                      0xffff8000
#define BCHP_XPT_RAVE_INT_CX23_reserved0_SHIFT                     15

/* XPT_RAVE :: INT_CX23 :: SCD_INDEX [14:12] */
#define BCHP_XPT_RAVE_INT_CX23_SCD_INDEX_MASK                      0x00007000
#define BCHP_XPT_RAVE_INT_CX23_SCD_INDEX_SHIFT                     12

/* XPT_RAVE :: INT_CX23 :: ITB_UPPER_THRESH_INT [11:11] */
#define BCHP_XPT_RAVE_INT_CX23_ITB_UPPER_THRESH_INT_MASK           0x00000800
#define BCHP_XPT_RAVE_INT_CX23_ITB_UPPER_THRESH_INT_SHIFT          11

/* XPT_RAVE :: INT_CX23 :: ITB_LOWER_THRESH_INT [10:10] */
#define BCHP_XPT_RAVE_INT_CX23_ITB_LOWER_THRESH_INT_MASK           0x00000400
#define BCHP_XPT_RAVE_INT_CX23_ITB_LOWER_THRESH_INT_SHIFT          10

/* XPT_RAVE :: INT_CX23 :: CDB_UPPER_THRESH_INT [09:09] */
#define BCHP_XPT_RAVE_INT_CX23_CDB_UPPER_THRESH_INT_MASK           0x00000200
#define BCHP_XPT_RAVE_INT_CX23_CDB_UPPER_THRESH_INT_SHIFT          9

/* XPT_RAVE :: INT_CX23 :: CDB_LOWER_THRESH_INT [08:08] */
#define BCHP_XPT_RAVE_INT_CX23_CDB_LOWER_THRESH_INT_MASK           0x00000100
#define BCHP_XPT_RAVE_INT_CX23_CDB_LOWER_THRESH_INT_SHIFT          8

/* XPT_RAVE :: INT_CX23 :: LAST_CMD_INT [07:07] */
#define BCHP_XPT_RAVE_INT_CX23_LAST_CMD_INT_MASK                   0x00000080
#define BCHP_XPT_RAVE_INT_CX23_LAST_CMD_INT_SHIFT                  7

/* XPT_RAVE :: INT_CX23 :: SPLICE_INT [06:06] */
#define BCHP_XPT_RAVE_INT_CX23_SPLICE_INT_MASK                     0x00000040
#define BCHP_XPT_RAVE_INT_CX23_SPLICE_INT_SHIFT                    6

/* XPT_RAVE :: INT_CX23 :: ITB_OVERFLOW_INT [05:05] */
#define BCHP_XPT_RAVE_INT_CX23_ITB_OVERFLOW_INT_MASK               0x00000020
#define BCHP_XPT_RAVE_INT_CX23_ITB_OVERFLOW_INT_SHIFT              5

/* XPT_RAVE :: INT_CX23 :: CDB_OVERFLOW_INT [04:04] */
#define BCHP_XPT_RAVE_INT_CX23_CDB_OVERFLOW_INT_MASK               0x00000010
#define BCHP_XPT_RAVE_INT_CX23_CDB_OVERFLOW_INT_SHIFT              4

/* XPT_RAVE :: INT_CX23 :: CC_ERROR_INT [03:03] */
#define BCHP_XPT_RAVE_INT_CX23_CC_ERROR_INT_MASK                   0x00000008
#define BCHP_XPT_RAVE_INT_CX23_CC_ERROR_INT_SHIFT                  3

/* XPT_RAVE :: INT_CX23 :: TEI_ERROR_INT [02:02] */
#define BCHP_XPT_RAVE_INT_CX23_TEI_ERROR_INT_MASK                  0x00000004
#define BCHP_XPT_RAVE_INT_CX23_TEI_ERROR_INT_SHIFT                 2

/* XPT_RAVE :: INT_CX23 :: PUSI_ERROR_INT [01:01] */
#define BCHP_XPT_RAVE_INT_CX23_PUSI_ERROR_INT_MASK                 0x00000002
#define BCHP_XPT_RAVE_INT_CX23_PUSI_ERROR_INT_SHIFT                1

/* XPT_RAVE :: INT_CX23 :: EMU_ERROR_INT [00:00] */
#define BCHP_XPT_RAVE_INT_CX23_EMU_ERROR_INT_MASK                  0x00000001
#define BCHP_XPT_RAVE_INT_CX23_EMU_ERROR_INT_SHIFT                 0

/***************************************************************************
 *INT_MISC - Miscellaneous Interrupts
 ***************************************************************************/
/* XPT_RAVE :: INT_MISC :: reserved0 [31:12] */
#define BCHP_XPT_RAVE_INT_MISC_reserved0_MASK                      0xfffff000
#define BCHP_XPT_RAVE_INT_MISC_reserved0_SHIFT                     12

/* XPT_RAVE :: INT_MISC :: reserved_for_eco1 [11:08] */
#define BCHP_XPT_RAVE_INT_MISC_reserved_for_eco1_MASK              0x00000f00
#define BCHP_XPT_RAVE_INT_MISC_reserved_for_eco1_SHIFT             8

/* XPT_RAVE :: INT_MISC :: MISC_INT7 [07:07] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT7_MASK                      0x00000080
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT7_SHIFT                     7

/* XPT_RAVE :: INT_MISC :: MISC_INT6 [06:06] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT6_MASK                      0x00000040
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT6_SHIFT                     6

/* XPT_RAVE :: INT_MISC :: MISC_INT5 [05:05] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT5_MASK                      0x00000020
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT5_SHIFT                     5

/* XPT_RAVE :: INT_MISC :: MISC_INT4 [04:04] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT4_MASK                      0x00000010
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT4_SHIFT                     4

/* XPT_RAVE :: INT_MISC :: MISC_INT3 [03:03] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT3_MASK                      0x00000008
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT3_SHIFT                     3

/* XPT_RAVE :: INT_MISC :: MISC_INT2 [02:02] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT2_MASK                      0x00000004
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT2_SHIFT                     2

/* XPT_RAVE :: INT_MISC :: MISC_INT1 [01:01] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT1_MASK                      0x00000002
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT1_SHIFT                     1

/* XPT_RAVE :: INT_MISC :: MISC_INT0 [00:00] */
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT0_MASK                      0x00000001
#define BCHP_XPT_RAVE_INT_MISC_MISC_INT0_SHIFT                     0

/***************************************************************************
 *CXMEM_LO%i - Context Table 0 (for contexts 0 - 15) 0..287
 ***************************************************************************/
#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_BASE                         0x00213200
#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_START                        0
#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_END                          287
#define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_ELEMENT_SIZE                 32

/***************************************************************************
 *CXMEM_LO%i - Context Table 0 (for contexts 0 - 15) 0..287
 ***************************************************************************/
/* XPT_RAVE :: CXMEM_LOi :: CX15_MAP_G [31:31] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_G_MASK                    0x80000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_G_SHIFT                   31

/* XPT_RAVE :: CXMEM_LOi :: CX15_MAP_R [30:30] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_R_MASK                    0x40000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_R_SHIFT                   30

/* XPT_RAVE :: CXMEM_LOi :: CX14_MAP_G [29:29] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_G_MASK                    0x20000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_G_SHIFT                   29

/* XPT_RAVE :: CXMEM_LOi :: CX14_MAP_R [28:28] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_R_MASK                    0x10000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_R_SHIFT                   28

/* XPT_RAVE :: CXMEM_LOi :: CX13_MAP_G [27:27] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_G_MASK                    0x08000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_G_SHIFT                   27

/* XPT_RAVE :: CXMEM_LOi :: CX13_MAP_R [26:26] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_R_MASK                    0x04000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_R_SHIFT                   26

/* XPT_RAVE :: CXMEM_LOi :: CX12_MAP_G [25:25] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_G_MASK                    0x02000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_G_SHIFT                   25

/* XPT_RAVE :: CXMEM_LOi :: CX12_MAP_R [24:24] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_R_MASK                    0x01000000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_R_SHIFT                   24

/* XPT_RAVE :: CXMEM_LOi :: CX11_MAP_G [23:23] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_G_MASK                    0x00800000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_G_SHIFT                   23

/* XPT_RAVE :: CXMEM_LOi :: CX11_MAP_R [22:22] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_R_MASK                    0x00400000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_R_SHIFT                   22

/* XPT_RAVE :: CXMEM_LOi :: CX10_MAP_G [21:21] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_G_MASK                    0x00200000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_G_SHIFT                   21

/* XPT_RAVE :: CXMEM_LOi :: CX10_MAP_R [20:20] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_R_MASK                    0x00100000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_R_SHIFT                   20

/* XPT_RAVE :: CXMEM_LOi :: CX9_MAP_G [19:19] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_G_MASK                     0x00080000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_G_SHIFT                    19

/* XPT_RAVE :: CXMEM_LOi :: CX9_MAP_R [18:18] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_R_MASK                     0x00040000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_R_SHIFT                    18

/* XPT_RAVE :: CXMEM_LOi :: CX8_MAP_G [17:17] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_G_MASK                     0x00020000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_G_SHIFT                    17

/* XPT_RAVE :: CXMEM_LOi :: CX8_MAP_R [16:16] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_R_MASK                     0x00010000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_R_SHIFT                    16

/* XPT_RAVE :: CXMEM_LOi :: CX7_MAP_G [15:15] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_G_MASK                     0x00008000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_G_SHIFT                    15

/* XPT_RAVE :: CXMEM_LOi :: CX7_MAP_R [14:14] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_R_MASK                     0x00004000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_R_SHIFT                    14

/* XPT_RAVE :: CXMEM_LOi :: CX6_MAP_G [13:13] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_G_MASK                     0x00002000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_G_SHIFT                    13

/* XPT_RAVE :: CXMEM_LOi :: CX6_MAP_R [12:12] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_R_MASK                     0x00001000
#define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_R_SHIFT                    12

/* XPT_RAVE :: CXMEM_LOi :: CX5_MAP_G [11:11] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_G_MASK                     0x00000800
#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_G_SHIFT                    11

/* XPT_RAVE :: CXMEM_LOi :: CX5_MAP_R [10:10] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_R_MASK                     0x00000400
#define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_R_SHIFT                    10

/* XPT_RAVE :: CXMEM_LOi :: CX4_MAP_G [09:09] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_G_MASK                     0x00000200
#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_G_SHIFT                    9

/* XPT_RAVE :: CXMEM_LOi :: CX4_MAP_R [08:08] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_R_MASK                     0x00000100
#define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_R_SHIFT                    8

/* XPT_RAVE :: CXMEM_LOi :: CX3_MAP_G [07:07] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_G_MASK                     0x00000080
#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_G_SHIFT                    7

/* XPT_RAVE :: CXMEM_LOi :: CX3_MAP_R [06:06] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_R_MASK                     0x00000040
#define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_R_SHIFT                    6

/* XPT_RAVE :: CXMEM_LOi :: CX2_MAP_G [05:05] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_G_MASK                     0x00000020
#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_G_SHIFT                    5

/* XPT_RAVE :: CXMEM_LOi :: CX2_MAP_R [04:04] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_R_MASK                     0x00000010
#define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_R_SHIFT                    4

/* XPT_RAVE :: CXMEM_LOi :: CX1_MAP_G [03:03] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_G_MASK                     0x00000008
#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_G_SHIFT                    3

/* XPT_RAVE :: CXMEM_LOi :: CX1_MAP_R [02:02] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_R_MASK                     0x00000004
#define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_R_SHIFT                    2

/* XPT_RAVE :: CXMEM_LOi :: CX0_MAP_G [01:01] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_G_MASK                     0x00000002
#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_G_SHIFT                    1

/* XPT_RAVE :: CXMEM_LOi :: CX0_MAP_R [00:00] */
#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_R_MASK                     0x00000001
#define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_R_SHIFT                    0


/***************************************************************************
 *CXMEM_HI%i - Context Table 1 (for contexts 16 - 23) 0..287
 ***************************************************************************/
#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_BASE                         0x00213800
#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_START                        0
#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_END                          287
#define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_ELEMENT_SIZE                 32

/***************************************************************************
 *CXMEM_HI%i - Context Table 1 (for contexts 16 - 23) 0..287
 ***************************************************************************/
/* XPT_RAVE :: CXMEM_HIi :: reserved_for_eco0 [31:16] */
#define BCHP_XPT_RAVE_CXMEM_HIi_reserved_for_eco0_MASK             0xffff0000
#define BCHP_XPT_RAVE_CXMEM_HIi_reserved_for_eco0_SHIFT            16

/* XPT_RAVE :: CXMEM_HIi :: CX23_MAP_G [15:15] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_G_MASK                    0x00008000
#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_G_SHIFT                   15

/* XPT_RAVE :: CXMEM_HIi :: CX23_MAP_R [14:14] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_R_MASK                    0x00004000
#define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_R_SHIFT                   14

/* XPT_RAVE :: CXMEM_HIi :: CX22_MAP_G [13:13] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_G_MASK                    0x00002000
#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_G_SHIFT                   13

/* XPT_RAVE :: CXMEM_HIi :: CX22_MAP_R [12:12] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_R_MASK                    0x00001000
#define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_R_SHIFT                   12

/* XPT_RAVE :: CXMEM_HIi :: CX21_MAP_G [11:11] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_G_MASK                    0x00000800
#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_G_SHIFT                   11

/* XPT_RAVE :: CXMEM_HIi :: CX21_MAP_R [10:10] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_R_MASK                    0x00000400
#define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_R_SHIFT                   10

/* XPT_RAVE :: CXMEM_HIi :: CX20_MAP_G [09:09] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_G_MASK                    0x00000200
#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_G_SHIFT                   9

/* XPT_RAVE :: CXMEM_HIi :: CX20_MAP_R [08:08] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_R_MASK                    0x00000100
#define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_R_SHIFT                   8

/* XPT_RAVE :: CXMEM_HIi :: CX19_MAP_G [07:07] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_G_MASK                    0x00000080
#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_G_SHIFT                   7

/* XPT_RAVE :: CXMEM_HIi :: CX19_MAP_R [06:06] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_R_MASK                    0x00000040
#define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_R_SHIFT                   6

/* XPT_RAVE :: CXMEM_HIi :: CX18_MAP_G [05:05] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_G_MASK                    0x00000020
#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_G_SHIFT                   5

/* XPT_RAVE :: CXMEM_HIi :: CX18_MAP_R [04:04] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_R_MASK                    0x00000010
#define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_R_SHIFT                   4

/* XPT_RAVE :: CXMEM_HIi :: CX17_MAP_G [03:03] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_G_MASK                    0x00000008
#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_G_SHIFT                   3

/* XPT_RAVE :: CXMEM_HIi :: CX17_MAP_R [02:02] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_R_MASK                    0x00000004
#define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_R_SHIFT                   2

/* XPT_RAVE :: CXMEM_HIi :: CX16_MAP_G [01:01] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_G_MASK                    0x00000002
#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_G_SHIFT                   1

/* XPT_RAVE :: CXMEM_HIi :: CX16_MAP_R [00:00] */
#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_R_MASK                    0x00000001
#define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_R_SHIFT                   0


/***************************************************************************
 *DMEM%i - Data Memory Address 0..2047
 ***************************************************************************/
#define BCHP_XPT_RAVE_DMEMi_ARRAY_BASE                             0x00214000
#define BCHP_XPT_RAVE_DMEMi_ARRAY_START                            0
#define BCHP_XPT_RAVE_DMEMi_ARRAY_END                              2047
#define BCHP_XPT_RAVE_DMEMi_ARRAY_ELEMENT_SIZE                     32

/***************************************************************************
 *DMEM%i - Data Memory Address 0..2047
 ***************************************************************************/
/* XPT_RAVE :: DMEMi :: reserved_for_eco0 [31:08] */
#define BCHP_XPT_RAVE_DMEMi_reserved_for_eco0_MASK                 0xffffff00
#define BCHP_XPT_RAVE_DMEMi_reserved_for_eco0_SHIFT                8

/* XPT_RAVE :: DMEMi :: DATA [07:00] */
#define BCHP_XPT_RAVE_DMEMi_DATA_MASK                              0x000000ff
#define BCHP_XPT_RAVE_DMEMi_DATA_SHIFT                             0


/***************************************************************************
 *EMM_TID_MODE - TPIT EMM_TID_MODE Register (NDS only)
 ***************************************************************************/
/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_F [31:30] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_F_MASK             0xc0000000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_F_SHIFT            30

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_E [29:28] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_E_MASK             0x30000000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_E_SHIFT            28

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_D [27:26] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_D_MASK             0x0c000000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_D_SHIFT            26

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_C [25:24] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_C_MASK             0x03000000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_C_SHIFT            24

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_B [23:22] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_B_MASK             0x00c00000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_B_SHIFT            22

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_A [21:20] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_A_MASK             0x00300000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_A_SHIFT            20

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_9 [19:18] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_9_MASK             0x000c0000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_9_SHIFT            18

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_8 [17:16] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_8_MASK             0x00030000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_8_SHIFT            16

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_7 [15:14] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_7_MASK             0x0000c000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_7_SHIFT            14

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_6 [13:12] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_6_MASK             0x00003000
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_6_SHIFT            12

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_5 [11:10] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_5_MASK             0x00000c00
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_5_SHIFT            10

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_4 [09:08] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_4_MASK             0x00000300
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_4_SHIFT            8

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_3 [07:06] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_3_MASK             0x000000c0
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_3_SHIFT            6

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_2 [05:04] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_2_MASK             0x00000030
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_2_SHIFT            4

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_1 [03:02] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_1_MASK             0x0000000c
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_1_SHIFT            2

/* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_0 [01:00] */
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_0_MASK             0x00000003
#define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_0_SHIFT            0

/***************************************************************************
 *EMM_DATA_ID_1 - TPIT EMM_DATA_ID_1 Register (NDS only)
 ***************************************************************************/
/* XPT_RAVE :: EMM_DATA_ID_1 :: EMM_DATA_ID_1 [31:00] */
#define BCHP_XPT_RAVE_EMM_DATA_ID_1_EMM_DATA_ID_1_MASK             0xffffffff
#define BCHP_XPT_RAVE_EMM_DATA_ID_1_EMM_DATA_ID_1_SHIFT            0

/***************************************************************************
 *EMM_DATA_ID_2 - TPIT EMM_DATA_ID_2 Register (NDS only)
 ***************************************************************************/
/* XPT_RAVE :: EMM_DATA_ID_2 :: EMM_DATA_ID_2 [31:00] */
#define BCHP_XPT_RAVE_EMM_DATA_ID_2_EMM_DATA_ID_2_MASK             0xffffffff
#define BCHP_XPT_RAVE_EMM_DATA_ID_2_EMM_DATA_ID_2_SHIFT            0

/***************************************************************************
 *EMM_DATA_ID_3 - TPIT EMM_DATA_ID_3 Register (NDS only)
 ***************************************************************************/
/* XPT_RAVE :: EMM_DATA_ID_3 :: EMM_DATA_ID_3 [31:00] */
#define BCHP_XPT_RAVE_EMM_DATA_ID_3_EMM_DATA_ID_3_MASK             0xffffffff
#define BCHP_XPT_RAVE_EMM_DATA_ID_3_EMM_DATA_ID_3_SHIFT            0

/***************************************************************************
 *EMM_MASK_ID_1 - TPIT EMM_MASK_ID_1 Register (NDS only)
 ***************************************************************************/
/* XPT_RAVE :: EMM_MASK_ID_1 :: EMM_DATA_MASK_ID_1 [31:00] */
#define BCHP_XPT_RAVE_EMM_MASK_ID_1_EMM_DATA_MASK_ID_1_MASK        0xffffffff
#define BCHP_XPT_RAVE_EMM_MASK_ID_1_EMM_DATA_MASK_ID_1_SHIFT       0

/***************************************************************************
 *EMM_MASK_ID_2 - TPIT EMM_MASK_ID_2 Register (NDS only)
 ***************************************************************************/
/* XPT_RAVE :: EMM_MASK_ID_2 :: EMM_DATA_MASK_ID_2 [31:00] */
#define BCHP_XPT_RAVE_EMM_MASK_ID_2_EMM_DATA_MASK_ID_2_MASK        0xffffffff
#define BCHP_XPT_RAVE_EMM_MASK_ID_2_EMM_DATA_MASK_ID_2_SHIFT       0

/***************************************************************************
 *EMM_MASK_ID_3 - TPIT EMM_MASK_ID_3 Register (NDS only)
 ***************************************************************************/
/* XPT_RAVE :: EMM_MASK_ID_3 :: EMM_DATA_MASK_ID_3 [31:00] */
#define BCHP_XPT_RAVE_EMM_MASK_ID_3_EMM_DATA_MASK_ID_3_MASK        0xffffffff
#define BCHP_XPT_RAVE_EMM_MASK_ID_3_EMM_DATA_MASK_ID_3_SHIFT       0

/***************************************************************************
 *TPIT_TIME_TICK - TPIT Time Tick Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT_TIME_TICK :: reserved0 [31:24] */
#define BCHP_XPT_RAVE_TPIT_TIME_TICK_reserved0_MASK                0xff000000
#define BCHP_XPT_RAVE_TPIT_TIME_TICK_reserved0_SHIFT               24

/* XPT_RAVE :: TPIT_TIME_TICK :: TPIT_TIME_TICK [23:00] */
#define BCHP_XPT_RAVE_TPIT_TIME_TICK_TPIT_TIME_TICK_MASK           0x00ffffff
#define BCHP_XPT_RAVE_TPIT_TIME_TICK_TPIT_TIME_TICK_SHIFT          0

/***************************************************************************
 *TPIT_PKT_TIMEOUT - TPIT Time Packet Timeout Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT_PKT_TIMEOUT :: reserved0 [31:24] */
#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_reserved0_MASK              0xff000000
#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_reserved0_SHIFT             24

/* XPT_RAVE :: TPIT_PKT_TIMEOUT :: TPIT_PKT_TIMEOUT [23:00] */
#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_TPIT_PKT_TIMEOUT_MASK       0x00ffffff
#define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_TPIT_PKT_TIMEOUT_SHIFT      0

/***************************************************************************
 *TPIT_EVE_TIMEOUT - TPIT Time Event Timeout Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT_EVE_TIMEOUT :: reserved0 [31:24] */
#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_reserved0_MASK              0xff000000
#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_reserved0_SHIFT             24

/* XPT_RAVE :: TPIT_EVE_TIMEOUT :: TPIT_EVE_TIMEOUT [23:00] */
#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_TPIT_EVE_TIMEOUT_MASK       0x00ffffff
#define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_TPIT_EVE_TIMEOUT_SHIFT      0

/***************************************************************************
 *TPIT0_PID_TABLE%i - TPIT0 PID Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_BASE                  0x0021a000
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT0_PID_TABLE%i - TPIT0 PID Table 0..15
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_PID_TABLEi :: reserved_for_eco0 [31:21] */
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco0_MASK      0xffe00000
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco0_SHIFT     21

/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_HD [20:17] */
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_MASK                 0x001e0000
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_SHIFT                17

/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_HD_FILT_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_FILT_EN_MASK         0x00010000
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_FILT_EN_SHIFT        16

/* XPT_RAVE :: TPIT0_PID_TABLEi :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco1_MASK      0x00008000
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco1_SHIFT     15

/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_CORRUPT_ENABLE_MASK     0x00004000
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT    14

/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PARSE_ENABLE_MASK       0x00002000
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PARSE_ENABLE_SHIFT      13

/* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_PID [12:00] */
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PID_MASK                0x00001fff
#define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PID_SHIFT               0


/***************************************************************************
 *TPIT0_PAR_TABLE%i - TPIT0 Parse Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_BASE                  0x0021a040
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT0_PAR_TABLE%i - TPIT0 Parse Table 0..15
 ***************************************************************************/
/* union - case MPEG [31:00] */
/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK   0x01000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT  24

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK    0x00800000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT   23

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK  0x00080000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK  0x00040000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK        0x00010000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT       16

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: reserved1 [15:13] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved1_MASK         0x0000e000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved1_SHIFT        13

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK  0x00000080
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: reserved0 [03:02] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved0_MASK         0x0000000c
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved0_SHIFT        2

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK      0x00000001
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT     0

/* union - case DIRECTV [31:00] */
/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved2_MASK      0xc0000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved2_SHIFT     30

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK  0x20000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK   0x10000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT  28

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK  0x08000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK  0x04000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK      0x02000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT     25

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK       0x01000000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT      24

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK       0x00f00000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT      20

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK       0x00010000
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT      16

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved1_MASK      0x0000fc00
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved1_SHIFT     10

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK    0x00000200
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT   9

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK     0x00000100
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT    8

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK     0x000000f0
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT    4

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved0_MASK      0x0000000e
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved0_SHIFT     1

/* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK     0x00000001
#define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT    0


/***************************************************************************
 *TPIT1_PID_TABLE%i - TPIT1 PID Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_BASE                  0x0021a080
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT1_PID_TABLE%i - TPIT1 PID Table 0..15
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_PID_TABLEi :: reserved_for_eco0 [31:21] */
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco0_MASK      0xffe00000
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco0_SHIFT     21

/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_HD [20:17] */
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_MASK                 0x001e0000
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_SHIFT                17

/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_HD_FILT_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_FILT_EN_MASK         0x00010000
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_FILT_EN_SHIFT        16

/* XPT_RAVE :: TPIT1_PID_TABLEi :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco1_MASK      0x00008000
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco1_SHIFT     15

/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_CORRUPT_ENABLE_MASK     0x00004000
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT    14

/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PARSE_ENABLE_MASK       0x00002000
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PARSE_ENABLE_SHIFT      13

/* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_PID [12:00] */
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PID_MASK                0x00001fff
#define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PID_SHIFT               0


/***************************************************************************
 *TPIT1_PAR_TABLE%i - TPIT1 Parse Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_BASE                  0x0021a0c0
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT1_PAR_TABLE%i - TPIT1 Parse Table 0..15
 ***************************************************************************/
/* union - case MPEG [31:00] */
/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK   0x01000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT  24

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK    0x00800000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT   23

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK  0x00080000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK  0x00040000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK        0x00010000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT       16

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: reserved1 [15:13] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved1_MASK         0x0000e000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved1_SHIFT        13

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK  0x00000080
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: reserved0 [03:02] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved0_MASK         0x0000000c
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved0_SHIFT        2

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK      0x00000001
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT     0

/* union - case DIRECTV [31:00] */
/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved2_MASK      0xc0000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved2_SHIFT     30

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK  0x20000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK   0x10000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT  28

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK  0x08000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK  0x04000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK      0x02000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT     25

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK       0x01000000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT      24

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK       0x00f00000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT      20

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK       0x00010000
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT      16

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved1_MASK      0x0000fc00
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved1_SHIFT     10

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK    0x00000200
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT   9

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK     0x00000100
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT    8

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK     0x000000f0
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT    4

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved0_MASK      0x0000000e
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved0_SHIFT     1

/* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK     0x00000001
#define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT    0


/***************************************************************************
 *TPIT2_PID_TABLE%i - TPIT2 PID Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_BASE                  0x0021a100
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT2_PID_TABLE%i - TPIT2 PID Table 0..15
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_PID_TABLEi :: reserved_for_eco0 [31:21] */
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco0_MASK      0xffe00000
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco0_SHIFT     21

/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_HD [20:17] */
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_MASK                 0x001e0000
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_SHIFT                17

/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_HD_FILT_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_FILT_EN_MASK         0x00010000
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_FILT_EN_SHIFT        16

/* XPT_RAVE :: TPIT2_PID_TABLEi :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco1_MASK      0x00008000
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco1_SHIFT     15

/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_CORRUPT_ENABLE_MASK     0x00004000
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT    14

/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PARSE_ENABLE_MASK       0x00002000
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PARSE_ENABLE_SHIFT      13

/* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_PID [12:00] */
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PID_MASK                0x00001fff
#define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PID_SHIFT               0


/***************************************************************************
 *TPIT2_PAR_TABLE%i - TPIT2 Parse Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_BASE                  0x0021a140
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT2_PAR_TABLE%i - TPIT2 Parse Table 0..15
 ***************************************************************************/
/* union - case MPEG [31:00] */
/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK   0x01000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT  24

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK    0x00800000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT   23

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK  0x00080000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK  0x00040000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK        0x00010000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT       16

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: reserved1 [15:13] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved1_MASK         0x0000e000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved1_SHIFT        13

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK  0x00000080
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: reserved0 [03:02] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved0_MASK         0x0000000c
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved0_SHIFT        2

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK      0x00000001
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT     0

/* union - case DIRECTV [31:00] */
/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved2_MASK      0xc0000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved2_SHIFT     30

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK  0x20000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK   0x10000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT  28

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK  0x08000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK  0x04000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK      0x02000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT     25

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK       0x01000000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT      24

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK       0x00f00000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT      20

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK       0x00010000
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT      16

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved1_MASK      0x0000fc00
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved1_SHIFT     10

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK    0x00000200
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT   9

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK     0x00000100
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT    8

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK     0x000000f0
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT    4

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved0_MASK      0x0000000e
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved0_SHIFT     1

/* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK     0x00000001
#define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT    0


/***************************************************************************
 *TPIT3_PID_TABLE%i - TPIT3 PID Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_BASE                  0x0021a180
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT3_PID_TABLE%i - TPIT3 PID Table 0..15
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_PID_TABLEi :: reserved_for_eco0 [31:21] */
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco0_MASK      0xffe00000
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco0_SHIFT     21

/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_HD [20:17] */
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_MASK                 0x001e0000
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_SHIFT                17

/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_HD_FILT_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_FILT_EN_MASK         0x00010000
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_FILT_EN_SHIFT        16

/* XPT_RAVE :: TPIT3_PID_TABLEi :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco1_MASK      0x00008000
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco1_SHIFT     15

/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_CORRUPT_ENABLE_MASK     0x00004000
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT    14

/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PARSE_ENABLE_MASK       0x00002000
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PARSE_ENABLE_SHIFT      13

/* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_PID [12:00] */
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PID_MASK                0x00001fff
#define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PID_SHIFT               0


/***************************************************************************
 *TPIT3_PAR_TABLE%i - TPIT3 Parse Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_BASE                  0x0021a1c0
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT3_PAR_TABLE%i - TPIT3 Parse Table 0..15
 ***************************************************************************/
/* union - case MPEG [31:00] */
/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK   0x01000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT  24

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK    0x00800000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT   23

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK  0x00080000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK  0x00040000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK        0x00010000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT       16

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: reserved1 [15:13] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved1_MASK         0x0000e000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved1_SHIFT        13

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK  0x00000080
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: reserved0 [03:02] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved0_MASK         0x0000000c
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved0_SHIFT        2

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK      0x00000001
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT     0

/* union - case DIRECTV [31:00] */
/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved2_MASK      0xc0000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved2_SHIFT     30

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK  0x20000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK   0x10000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT  28

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK  0x08000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK  0x04000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK      0x02000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT     25

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK       0x01000000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT      24

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK       0x00f00000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT      20

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK       0x00010000
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT      16

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved1_MASK      0x0000fc00
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved1_SHIFT     10

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK    0x00000200
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT   9

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK     0x00000100
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT    8

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK     0x000000f0
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT    4

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved0_MASK      0x0000000e
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved0_SHIFT     1

/* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK     0x00000001
#define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT    0


/***************************************************************************
 *TPIT4_PID_TABLE%i - TPIT4 PID Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_BASE                  0x0021a200
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT4_PID_TABLE%i - TPIT4 PID Table 0..15
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_PID_TABLEi :: reserved_for_eco0 [31:21] */
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco0_MASK      0xffe00000
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco0_SHIFT     21

/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_HD [20:17] */
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_MASK                 0x001e0000
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_SHIFT                17

/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_HD_FILT_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_FILT_EN_MASK         0x00010000
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_FILT_EN_SHIFT        16

/* XPT_RAVE :: TPIT4_PID_TABLEi :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco1_MASK      0x00008000
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco1_SHIFT     15

/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_CORRUPT_ENABLE_MASK     0x00004000
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT    14

/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PARSE_ENABLE_MASK       0x00002000
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PARSE_ENABLE_SHIFT      13

/* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_PID [12:00] */
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PID_MASK                0x00001fff
#define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PID_SHIFT               0


/***************************************************************************
 *TPIT4_PAR_TABLE%i - TPIT4 Parse Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_BASE                  0x0021a240
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT4_PAR_TABLE%i - TPIT4 Parse Table 0..15
 ***************************************************************************/
/* union - case MPEG [31:00] */
/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK   0x01000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT  24

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK    0x00800000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT   23

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK  0x00080000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK  0x00040000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK        0x00010000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT       16

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: reserved1 [15:13] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved1_MASK         0x0000e000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved1_SHIFT        13

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK  0x00000080
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: reserved0 [03:02] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved0_MASK         0x0000000c
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved0_SHIFT        2

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK      0x00000001
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT     0

/* union - case DIRECTV [31:00] */
/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved2_MASK      0xc0000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved2_SHIFT     30

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK  0x20000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK   0x10000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT  28

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK  0x08000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK  0x04000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK      0x02000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT     25

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK       0x01000000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT      24

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK       0x00f00000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT      20

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK       0x00010000
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT      16

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved1_MASK      0x0000fc00
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved1_SHIFT     10

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK    0x00000200
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT   9

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK     0x00000100
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT    8

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK     0x000000f0
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT    4

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved0_MASK      0x0000000e
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved0_SHIFT     1

/* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK     0x00000001
#define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT    0


/***************************************************************************
 *TPIT5_PID_TABLE%i - TPIT5 PID Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_BASE                  0x0021a280
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT5_PID_TABLE%i - TPIT5 PID Table 0..15
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_PID_TABLEi :: reserved_for_eco0 [31:21] */
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco0_MASK      0xffe00000
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco0_SHIFT     21

/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_HD [20:17] */
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_MASK                 0x001e0000
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_SHIFT                17

/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_HD_FILT_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_FILT_EN_MASK         0x00010000
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_FILT_EN_SHIFT        16

/* XPT_RAVE :: TPIT5_PID_TABLEi :: reserved_for_eco1 [15:15] */
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco1_MASK      0x00008000
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco1_SHIFT     15

/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_CORRUPT_ENABLE_MASK     0x00004000
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT    14

/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PARSE_ENABLE_MASK       0x00002000
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PARSE_ENABLE_SHIFT      13

/* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_PID [12:00] */
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PID_MASK                0x00001fff
#define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PID_SHIFT               0


/***************************************************************************
 *TPIT5_PAR_TABLE%i - TPIT5 Parse Table 0..15
 ***************************************************************************/
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_BASE                  0x0021a2c0
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_START                 0
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_END                   15
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_ELEMENT_SIZE          32

/***************************************************************************
 *TPIT5_PAR_TABLE%i - TPIT5 Parse Table 0..15
 ***************************************************************************/
/* union - case MPEG [31:00] */
/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK   0x01000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT  24

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK    0x00800000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT   23

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK  0x00080000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK  0x00040000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK        0x00010000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT       16

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: reserved1 [15:13] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved1_MASK         0x0000e000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved1_SHIFT        13

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK  0x00000080
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: reserved0 [03:02] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved0_MASK         0x0000000c
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved0_SHIFT        2

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK      0x00000001
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT     0

/* union - case DIRECTV [31:00] */
/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved2_MASK      0xc0000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved2_SHIFT     30

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK  0x20000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK   0x10000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT  28

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK  0x08000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK  0x04000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK      0x02000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT     25

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK       0x01000000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT      24

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK       0x00f00000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT      20

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK       0x00010000
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT      16

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved1_MASK      0x0000fc00
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved1_SHIFT     10

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK    0x00000200
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT   9

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK     0x00000100
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT    8

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK     0x000000f0
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT    4

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved0_MASK      0x0000000e
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved0_SHIFT     1

/* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK     0x00000001
#define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT    0


/***************************************************************************
 *TPIT0_CTRL1 - TPIT 0 Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_CTRL1 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_reserved_for_eco0_MASK           0xfffffe00
#define BCHP_XPT_RAVE_TPIT0_CTRL1_reserved_for_eco0_SHIFT          9

/* XPT_RAVE :: TPIT0_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK       0x00000100
#define BCHP_XPT_RAVE_TPIT0_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT      8

/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_TIME_TICK_EN_MASK           0x00000080
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_TIME_TICK_EN_SHIFT          7

/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_SPAN_SECTION_EN_MASK        0x00000060
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT       5

/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_PCR_MODE [04:04] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_PCR_MODE_MASK               0x00000010
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_PCR_MODE_SHIFT              4

/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EVENT_IDLE_EN_MASK          0x00000008
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT         3

/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_EMM_TID_EN [02:02] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EMM_TID_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EMM_TID_EN_SHIFT            2

/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_RECORD_IDLE_EN_MASK         0x00000002
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT        1

/* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_FIRST_PACKET_EN_MASK        0x00000001
#define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT       0

/***************************************************************************
 *TPIT0_COR1 - TPIT 0 Corrupt Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_COR1 :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT0_COR1_reserved_for_eco0_MASK            0xff000000
#define BCHP_XPT_RAVE_TPIT0_COR1_reserved_for_eco0_SHIFT           24

/* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_BYTE [23:16] */
#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_BYTE_MASK             0x00ff0000
#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_BYTE_SHIFT            16

/* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_START [15:08] */
#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_START_MASK            0x0000ff00
#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_START_SHIFT           8

/* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_END [07:00] */
#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_END_MASK              0x000000ff
#define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_END_SHIFT             0

/***************************************************************************
 *TPIT0_TID - TPIT TID Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_TID :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco0_MASK             0xff000000
#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco0_SHIFT            24

/* XPT_RAVE :: TPIT0_TID :: ECM_TID_ODD [23:16] */
#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_ODD_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_ODD_SHIFT                  16

/* XPT_RAVE :: TPIT0_TID :: ECM_TID_EVEN [15:08] */
#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_EVEN_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_EVEN_SHIFT                 8

/* XPT_RAVE :: TPIT0_TID :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco1_MASK             0x000000f0
#define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco1_SHIFT            4

/* XPT_RAVE :: TPIT0_TID :: EMM_TID [03:00] */
#define BCHP_XPT_RAVE_TPIT0_TID_EMM_TID_MASK                       0x0000000f
#define BCHP_XPT_RAVE_TPIT0_TID_EMM_TID_SHIFT                      0

/***************************************************************************
 *TPIT0_TID2 - TPIT TID Register 2
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_ODD3 [31:24] */
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD3_MASK                 0xff000000
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD3_SHIFT                24

/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_EVEN3 [23:16] */
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN3_MASK                0x00ff0000
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN3_SHIFT               16

/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_ODD2 [15:08] */
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD2_MASK                 0x0000ff00
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD2_SHIFT                8

/* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_EVEN2 [07:00] */
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN2_MASK                0x000000ff
#define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN2_SHIFT               0

/***************************************************************************
 *TPIT0_STATE0 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE0 :: TPIT_TRACK_STATE0 [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE0_TPIT_TRACK_STATE0_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE0_TPIT_TRACK_STATE0_SHIFT         0

/***************************************************************************
 *TPIT0_STATE1 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE1 :: TPIT_TRACK_STATE1 [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE1_TPIT_TRACK_STATE1_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE1_TPIT_TRACK_STATE1_SHIFT         0

/***************************************************************************
 *TPIT0_STATE2 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE2 :: TPIT_TRACK_STATE2 [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE2_TPIT_TRACK_STATE2_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE2_TPIT_TRACK_STATE2_SHIFT         0

/***************************************************************************
 *TPIT0_STATE2a - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE2a :: TPIT_TRACK_STATE2a [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE2a_TPIT_TRACK_STATE2a_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE2a_TPIT_TRACK_STATE2a_SHIFT       0

/***************************************************************************
 *TPIT0_STATE2b - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE2b :: TPIT_TRACK_STATE2b [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE2b_TPIT_TRACK_STATE2b_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE2b_TPIT_TRACK_STATE2b_SHIFT       0

/***************************************************************************
 *TPIT0_STATE2c - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE2c :: TPIT_TRACK_STATE2c [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE2c_TPIT_TRACK_STATE2c_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE2c_TPIT_TRACK_STATE2c_SHIFT       0

/***************************************************************************
 *TPIT0_STATE2d - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE2d :: TPIT_TRACK_STATE2d [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE2d_TPIT_TRACK_STATE2d_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE2d_TPIT_TRACK_STATE2d_SHIFT       0

/***************************************************************************
 *TPIT0_STATE3 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE3 :: TPIT_TRACK_STATE3 [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE3_TPIT_TRACK_STATE3_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE3_TPIT_TRACK_STATE3_SHIFT         0

/***************************************************************************
 *TPIT0_STATE4 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE4 :: TPIT_CUR_PCR [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE4_TPIT_CUR_PCR_MASK               0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE4_TPIT_CUR_PCR_SHIFT              0

/***************************************************************************
 *TPIT0_STATE5 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE5_TPIT_LAST_PACKET_LO_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE5_TPIT_LAST_PACKET_LO_SHIFT       0

/***************************************************************************
 *TPIT0_STATE6 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE6_TPIT_LAST_EVENT_LO_MASK         0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE6_TPIT_LAST_EVENT_LO_SHIFT        0

/***************************************************************************
 *TPIT0_STATE7 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE7 :: reserved_for_eco0 [31:20] */
#define BCHP_XPT_RAVE_TPIT0_STATE7_reserved_for_eco0_MASK          0xfff00000
#define BCHP_XPT_RAVE_TPIT0_STATE7_reserved_for_eco0_SHIFT         20

/* XPT_RAVE :: TPIT0_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */
#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_EVENT_HI_MASK         0x000ffc00
#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_EVENT_HI_SHIFT        10

/* XPT_RAVE :: TPIT0_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_PACKET_HI_MASK        0x000003ff
#define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_PACKET_HI_SHIFT       0

/***************************************************************************
 *TPIT0_STATE8 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE8 :: TPIT_LAST_TICK_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE8_TPIT_LAST_TICK_LO_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT0_STATE8_TPIT_LAST_TICK_LO_SHIFT         0

/***************************************************************************
 *TPIT0_STATE9 - TPIT 0 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT0_STATE9 :: reserved_for_eco0 [31:10] */
#define BCHP_XPT_RAVE_TPIT0_STATE9_reserved_for_eco0_MASK          0xfffffc00
#define BCHP_XPT_RAVE_TPIT0_STATE9_reserved_for_eco0_SHIFT         10

/* XPT_RAVE :: TPIT0_STATE9 :: TPIT_LAST_TICK_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT0_STATE9_TPIT_LAST_TICK_HI_MASK          0x000003ff
#define BCHP_XPT_RAVE_TPIT0_STATE9_TPIT_LAST_TICK_HI_SHIFT         0

/***************************************************************************
 *TPIT1_CTRL1 - TPIT 1 Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_CTRL1 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_reserved_for_eco0_MASK           0xfffffe00
#define BCHP_XPT_RAVE_TPIT1_CTRL1_reserved_for_eco0_SHIFT          9

/* XPT_RAVE :: TPIT1_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK       0x00000100
#define BCHP_XPT_RAVE_TPIT1_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT      8

/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_TIME_TICK_EN_MASK           0x00000080
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_TIME_TICK_EN_SHIFT          7

/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_SPAN_SECTION_EN_MASK        0x00000060
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT       5

/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_PCR_MODE [04:04] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_PCR_MODE_MASK               0x00000010
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_PCR_MODE_SHIFT              4

/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EVENT_IDLE_EN_MASK          0x00000008
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT         3

/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_EMM_TID_EN [02:02] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EMM_TID_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EMM_TID_EN_SHIFT            2

/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_RECORD_IDLE_EN_MASK         0x00000002
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT        1

/* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_FIRST_PACKET_EN_MASK        0x00000001
#define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT       0

/***************************************************************************
 *TPIT1_COR1 - TPIT 1 Corrupt Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_COR1 :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT1_COR1_reserved_for_eco0_MASK            0xff000000
#define BCHP_XPT_RAVE_TPIT1_COR1_reserved_for_eco0_SHIFT           24

/* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_BYTE [23:16] */
#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_BYTE_MASK             0x00ff0000
#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_BYTE_SHIFT            16

/* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_START [15:08] */
#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_START_MASK            0x0000ff00
#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_START_SHIFT           8

/* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_END [07:00] */
#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_END_MASK              0x000000ff
#define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_END_SHIFT             0

/***************************************************************************
 *TPIT1_TID - TPIT TID Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_TID :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco0_MASK             0xff000000
#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco0_SHIFT            24

/* XPT_RAVE :: TPIT1_TID :: ECM_TID_ODD [23:16] */
#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_ODD_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_ODD_SHIFT                  16

/* XPT_RAVE :: TPIT1_TID :: ECM_TID_EVEN [15:08] */
#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_EVEN_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_EVEN_SHIFT                 8

/* XPT_RAVE :: TPIT1_TID :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco1_MASK             0x000000f0
#define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco1_SHIFT            4

/* XPT_RAVE :: TPIT1_TID :: EMM_TID [03:00] */
#define BCHP_XPT_RAVE_TPIT1_TID_EMM_TID_MASK                       0x0000000f
#define BCHP_XPT_RAVE_TPIT1_TID_EMM_TID_SHIFT                      0

/***************************************************************************
 *TPIT1_TID2 - TPIT TID Register 2
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_ODD3 [31:24] */
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD3_MASK                 0xff000000
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD3_SHIFT                24

/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_EVEN3 [23:16] */
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN3_MASK                0x00ff0000
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN3_SHIFT               16

/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_ODD2 [15:08] */
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD2_MASK                 0x0000ff00
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD2_SHIFT                8

/* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_EVEN2 [07:00] */
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN2_MASK                0x000000ff
#define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN2_SHIFT               0

/***************************************************************************
 *TPIT1_STATE0 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE0 :: TPIT_TRACK_STATE0 [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE0_TPIT_TRACK_STATE0_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE0_TPIT_TRACK_STATE0_SHIFT         0

/***************************************************************************
 *TPIT1_STATE1 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE1 :: TPIT_TRACK_STATE1 [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE1_TPIT_TRACK_STATE1_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE1_TPIT_TRACK_STATE1_SHIFT         0

/***************************************************************************
 *TPIT1_STATE2 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE2 :: TPIT_TRACK_STATE2 [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE2_TPIT_TRACK_STATE2_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE2_TPIT_TRACK_STATE2_SHIFT         0

/***************************************************************************
 *TPIT1_STATE2a - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE2a :: TPIT_TRACK_STATE2a [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE2a_TPIT_TRACK_STATE2a_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE2a_TPIT_TRACK_STATE2a_SHIFT       0

/***************************************************************************
 *TPIT1_STATE2b - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE2b :: TPIT_TRACK_STATE2b [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE2b_TPIT_TRACK_STATE2b_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE2b_TPIT_TRACK_STATE2b_SHIFT       0

/***************************************************************************
 *TPIT1_STATE2c - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE2c :: TPIT_TRACK_STATE2c [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE2c_TPIT_TRACK_STATE2c_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE2c_TPIT_TRACK_STATE2c_SHIFT       0

/***************************************************************************
 *TPIT1_STATE2d - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE2d :: TPIT_TRACK_STATE2d [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE2d_TPIT_TRACK_STATE2d_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE2d_TPIT_TRACK_STATE2d_SHIFT       0

/***************************************************************************
 *TPIT1_STATE3 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE3 :: TPIT_TRACK_STATE3 [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE3_TPIT_TRACK_STATE3_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE3_TPIT_TRACK_STATE3_SHIFT         0

/***************************************************************************
 *TPIT1_STATE4 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE4 :: TPIT_CUR_PCR [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE4_TPIT_CUR_PCR_MASK               0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE4_TPIT_CUR_PCR_SHIFT              0

/***************************************************************************
 *TPIT1_STATE5 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE5_TPIT_LAST_PACKET_LO_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE5_TPIT_LAST_PACKET_LO_SHIFT       0

/***************************************************************************
 *TPIT1_STATE6 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE6_TPIT_LAST_EVENT_LO_MASK         0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE6_TPIT_LAST_EVENT_LO_SHIFT        0

/***************************************************************************
 *TPIT1_STATE7 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE7 :: reserved_for_eco0 [31:20] */
#define BCHP_XPT_RAVE_TPIT1_STATE7_reserved_for_eco0_MASK          0xfff00000
#define BCHP_XPT_RAVE_TPIT1_STATE7_reserved_for_eco0_SHIFT         20

/* XPT_RAVE :: TPIT1_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */
#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_EVENT_HI_MASK         0x000ffc00
#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_EVENT_HI_SHIFT        10

/* XPT_RAVE :: TPIT1_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_PACKET_HI_MASK        0x000003ff
#define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_PACKET_HI_SHIFT       0

/***************************************************************************
 *TPIT1_STATE8 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE8 :: TPIT_LAST_TICK_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE8_TPIT_LAST_TICK_LO_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT1_STATE8_TPIT_LAST_TICK_LO_SHIFT         0

/***************************************************************************
 *TPIT1_STATE9 - TPIT 1 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT1_STATE9 :: reserved_for_eco0 [31:10] */
#define BCHP_XPT_RAVE_TPIT1_STATE9_reserved_for_eco0_MASK          0xfffffc00
#define BCHP_XPT_RAVE_TPIT1_STATE9_reserved_for_eco0_SHIFT         10

/* XPT_RAVE :: TPIT1_STATE9 :: TPIT_LAST_TICK_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT1_STATE9_TPIT_LAST_TICK_HI_MASK          0x000003ff
#define BCHP_XPT_RAVE_TPIT1_STATE9_TPIT_LAST_TICK_HI_SHIFT         0

/***************************************************************************
 *TPIT2_CTRL1 - TPIT 2 Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_CTRL1 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_reserved_for_eco0_MASK           0xfffffe00
#define BCHP_XPT_RAVE_TPIT2_CTRL1_reserved_for_eco0_SHIFT          9

/* XPT_RAVE :: TPIT2_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK       0x00000100
#define BCHP_XPT_RAVE_TPIT2_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT      8

/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_TIME_TICK_EN_MASK           0x00000080
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_TIME_TICK_EN_SHIFT          7

/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_SPAN_SECTION_EN_MASK        0x00000060
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT       5

/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_PCR_MODE [04:04] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_PCR_MODE_MASK               0x00000010
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_PCR_MODE_SHIFT              4

/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EVENT_IDLE_EN_MASK          0x00000008
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT         3

/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_EMM_TID_EN [02:02] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EMM_TID_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EMM_TID_EN_SHIFT            2

/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_RECORD_IDLE_EN_MASK         0x00000002
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT        1

/* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_FIRST_PACKET_EN_MASK        0x00000001
#define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT       0

/***************************************************************************
 *TPIT2_COR1 - TPIT 2 Corrupt Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_COR1 :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT2_COR1_reserved_for_eco0_MASK            0xff000000
#define BCHP_XPT_RAVE_TPIT2_COR1_reserved_for_eco0_SHIFT           24

/* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_BYTE [23:16] */
#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_BYTE_MASK             0x00ff0000
#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_BYTE_SHIFT            16

/* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_START [15:08] */
#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_START_MASK            0x0000ff00
#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_START_SHIFT           8

/* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_END [07:00] */
#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_END_MASK              0x000000ff
#define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_END_SHIFT             0

/***************************************************************************
 *TPIT2_TID - TPIT TID Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_TID :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco0_MASK             0xff000000
#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco0_SHIFT            24

/* XPT_RAVE :: TPIT2_TID :: ECM_TID_ODD [23:16] */
#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_ODD_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_ODD_SHIFT                  16

/* XPT_RAVE :: TPIT2_TID :: ECM_TID_EVEN [15:08] */
#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_EVEN_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_EVEN_SHIFT                 8

/* XPT_RAVE :: TPIT2_TID :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco1_MASK             0x000000f0
#define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco1_SHIFT            4

/* XPT_RAVE :: TPIT2_TID :: EMM_TID [03:00] */
#define BCHP_XPT_RAVE_TPIT2_TID_EMM_TID_MASK                       0x0000000f
#define BCHP_XPT_RAVE_TPIT2_TID_EMM_TID_SHIFT                      0

/***************************************************************************
 *TPIT2_TID2 - TPIT TID Register 2
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_ODD3 [31:24] */
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD3_MASK                 0xff000000
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD3_SHIFT                24

/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_EVEN3 [23:16] */
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN3_MASK                0x00ff0000
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN3_SHIFT               16

/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_ODD2 [15:08] */
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD2_MASK                 0x0000ff00
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD2_SHIFT                8

/* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_EVEN2 [07:00] */
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN2_MASK                0x000000ff
#define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN2_SHIFT               0

/***************************************************************************
 *TPIT2_STATE0 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE0 :: TPIT_TRACK_STATE0 [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE0_TPIT_TRACK_STATE0_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE0_TPIT_TRACK_STATE0_SHIFT         0

/***************************************************************************
 *TPIT2_STATE1 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE1 :: TPIT_TRACK_STATE1 [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE1_TPIT_TRACK_STATE1_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE1_TPIT_TRACK_STATE1_SHIFT         0

/***************************************************************************
 *TPIT2_STATE2 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE2 :: TPIT_TRACK_STATE2 [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE2_TPIT_TRACK_STATE2_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE2_TPIT_TRACK_STATE2_SHIFT         0

/***************************************************************************
 *TPIT2_STATE2a - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE2a :: TPIT_TRACK_STATE2a [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE2a_TPIT_TRACK_STATE2a_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE2a_TPIT_TRACK_STATE2a_SHIFT       0

/***************************************************************************
 *TPIT2_STATE2b - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE2b :: TPIT_TRACK_STATE2b [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE2b_TPIT_TRACK_STATE2b_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE2b_TPIT_TRACK_STATE2b_SHIFT       0

/***************************************************************************
 *TPIT2_STATE2c - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE2c :: TPIT_TRACK_STATE2c [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE2c_TPIT_TRACK_STATE2c_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE2c_TPIT_TRACK_STATE2c_SHIFT       0

/***************************************************************************
 *TPIT2_STATE2d - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE2d :: TPIT_TRACK_STATE2d [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE2d_TPIT_TRACK_STATE2d_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE2d_TPIT_TRACK_STATE2d_SHIFT       0

/***************************************************************************
 *TPIT2_STATE3 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE3 :: TPIT_TRACK_STATE3 [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE3_TPIT_TRACK_STATE3_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE3_TPIT_TRACK_STATE3_SHIFT         0

/***************************************************************************
 *TPIT2_STATE4 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE4 :: TPIT_CUR_PCR [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE4_TPIT_CUR_PCR_MASK               0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE4_TPIT_CUR_PCR_SHIFT              0

/***************************************************************************
 *TPIT2_STATE5 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE5_TPIT_LAST_PACKET_LO_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE5_TPIT_LAST_PACKET_LO_SHIFT       0

/***************************************************************************
 *TPIT2_STATE6 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE6_TPIT_LAST_EVENT_LO_MASK         0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE6_TPIT_LAST_EVENT_LO_SHIFT        0

/***************************************************************************
 *TPIT2_STATE7 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE7 :: reserved_for_eco0 [31:20] */
#define BCHP_XPT_RAVE_TPIT2_STATE7_reserved_for_eco0_MASK          0xfff00000
#define BCHP_XPT_RAVE_TPIT2_STATE7_reserved_for_eco0_SHIFT         20

/* XPT_RAVE :: TPIT2_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */
#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_EVENT_HI_MASK         0x000ffc00
#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_EVENT_HI_SHIFT        10

/* XPT_RAVE :: TPIT2_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_PACKET_HI_MASK        0x000003ff
#define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_PACKET_HI_SHIFT       0

/***************************************************************************
 *TPIT2_STATE8 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE8 :: TPIT_LAST_TICK_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE8_TPIT_LAST_TICK_LO_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT2_STATE8_TPIT_LAST_TICK_LO_SHIFT         0

/***************************************************************************
 *TPIT2_STATE9 - TPIT 2 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT2_STATE9 :: reserved_for_eco0 [31:10] */
#define BCHP_XPT_RAVE_TPIT2_STATE9_reserved_for_eco0_MASK          0xfffffc00
#define BCHP_XPT_RAVE_TPIT2_STATE9_reserved_for_eco0_SHIFT         10

/* XPT_RAVE :: TPIT2_STATE9 :: TPIT_LAST_TICK_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT2_STATE9_TPIT_LAST_TICK_HI_MASK          0x000003ff
#define BCHP_XPT_RAVE_TPIT2_STATE9_TPIT_LAST_TICK_HI_SHIFT         0

/***************************************************************************
 *TPIT3_CTRL1 - TPIT 3 Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_CTRL1 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_reserved_for_eco0_MASK           0xfffffe00
#define BCHP_XPT_RAVE_TPIT3_CTRL1_reserved_for_eco0_SHIFT          9

/* XPT_RAVE :: TPIT3_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK       0x00000100
#define BCHP_XPT_RAVE_TPIT3_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT      8

/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_TIME_TICK_EN_MASK           0x00000080
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_TIME_TICK_EN_SHIFT          7

/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_SPAN_SECTION_EN_MASK        0x00000060
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT       5

/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_PCR_MODE [04:04] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_PCR_MODE_MASK               0x00000010
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_PCR_MODE_SHIFT              4

/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EVENT_IDLE_EN_MASK          0x00000008
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT         3

/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_EMM_TID_EN [02:02] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EMM_TID_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EMM_TID_EN_SHIFT            2

/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_RECORD_IDLE_EN_MASK         0x00000002
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT        1

/* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_FIRST_PACKET_EN_MASK        0x00000001
#define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT       0

/***************************************************************************
 *TPIT3_COR1 - TPIT 3 Corrupt Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_COR1 :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT3_COR1_reserved_for_eco0_MASK            0xff000000
#define BCHP_XPT_RAVE_TPIT3_COR1_reserved_for_eco0_SHIFT           24

/* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_BYTE [23:16] */
#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_BYTE_MASK             0x00ff0000
#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_BYTE_SHIFT            16

/* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_START [15:08] */
#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_START_MASK            0x0000ff00
#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_START_SHIFT           8

/* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_END [07:00] */
#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_END_MASK              0x000000ff
#define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_END_SHIFT             0

/***************************************************************************
 *TPIT3_TID - TPIT TID Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_TID :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco0_MASK             0xff000000
#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco0_SHIFT            24

/* XPT_RAVE :: TPIT3_TID :: ECM_TID_ODD [23:16] */
#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_ODD_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_ODD_SHIFT                  16

/* XPT_RAVE :: TPIT3_TID :: ECM_TID_EVEN [15:08] */
#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_EVEN_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_EVEN_SHIFT                 8

/* XPT_RAVE :: TPIT3_TID :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco1_MASK             0x000000f0
#define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco1_SHIFT            4

/* XPT_RAVE :: TPIT3_TID :: EMM_TID [03:00] */
#define BCHP_XPT_RAVE_TPIT3_TID_EMM_TID_MASK                       0x0000000f
#define BCHP_XPT_RAVE_TPIT3_TID_EMM_TID_SHIFT                      0

/***************************************************************************
 *TPIT3_TID2 - TPIT TID Register 2
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_ODD3 [31:24] */
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD3_MASK                 0xff000000
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD3_SHIFT                24

/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_EVEN3 [23:16] */
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN3_MASK                0x00ff0000
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN3_SHIFT               16

/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_ODD2 [15:08] */
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD2_MASK                 0x0000ff00
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD2_SHIFT                8

/* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_EVEN2 [07:00] */
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN2_MASK                0x000000ff
#define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN2_SHIFT               0

/***************************************************************************
 *TPIT3_STATE0 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE0 :: TPIT_TRACK_STATE0 [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE0_TPIT_TRACK_STATE0_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE0_TPIT_TRACK_STATE0_SHIFT         0

/***************************************************************************
 *TPIT3_STATE1 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE1 :: TPIT_TRACK_STATE1 [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE1_TPIT_TRACK_STATE1_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE1_TPIT_TRACK_STATE1_SHIFT         0

/***************************************************************************
 *TPIT3_STATE2 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE2 :: TPIT_TRACK_STATE2 [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE2_TPIT_TRACK_STATE2_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE2_TPIT_TRACK_STATE2_SHIFT         0

/***************************************************************************
 *TPIT3_STATE2a - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE2a :: TPIT_TRACK_STATE2a [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE2a_TPIT_TRACK_STATE2a_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE2a_TPIT_TRACK_STATE2a_SHIFT       0

/***************************************************************************
 *TPIT3_STATE2b - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE2b :: TPIT_TRACK_STATE2b [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE2b_TPIT_TRACK_STATE2b_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE2b_TPIT_TRACK_STATE2b_SHIFT       0

/***************************************************************************
 *TPIT3_STATE2c - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE2c :: TPIT_TRACK_STATE2c [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE2c_TPIT_TRACK_STATE2c_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE2c_TPIT_TRACK_STATE2c_SHIFT       0

/***************************************************************************
 *TPIT3_STATE2d - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE2d :: TPIT_TRACK_STATE2d [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE2d_TPIT_TRACK_STATE2d_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE2d_TPIT_TRACK_STATE2d_SHIFT       0

/***************************************************************************
 *TPIT3_STATE3 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE3 :: TPIT_TRACK_STATE3 [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE3_TPIT_TRACK_STATE3_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE3_TPIT_TRACK_STATE3_SHIFT         0

/***************************************************************************
 *TPIT3_STATE4 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE4 :: TPIT_CUR_PCR [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE4_TPIT_CUR_PCR_MASK               0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE4_TPIT_CUR_PCR_SHIFT              0

/***************************************************************************
 *TPIT3_STATE5 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE5_TPIT_LAST_PACKET_LO_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE5_TPIT_LAST_PACKET_LO_SHIFT       0

/***************************************************************************
 *TPIT3_STATE6 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE6_TPIT_LAST_EVENT_LO_MASK         0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE6_TPIT_LAST_EVENT_LO_SHIFT        0

/***************************************************************************
 *TPIT3_STATE7 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE7 :: reserved_for_eco0 [31:20] */
#define BCHP_XPT_RAVE_TPIT3_STATE7_reserved_for_eco0_MASK          0xfff00000
#define BCHP_XPT_RAVE_TPIT3_STATE7_reserved_for_eco0_SHIFT         20

/* XPT_RAVE :: TPIT3_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */
#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_EVENT_HI_MASK         0x000ffc00
#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_EVENT_HI_SHIFT        10

/* XPT_RAVE :: TPIT3_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_PACKET_HI_MASK        0x000003ff
#define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_PACKET_HI_SHIFT       0

/***************************************************************************
 *TPIT3_STATE8 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE8 :: TPIT_LAST_TICK_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE8_TPIT_LAST_TICK_LO_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT3_STATE8_TPIT_LAST_TICK_LO_SHIFT         0

/***************************************************************************
 *TPIT3_STATE9 - TPIT 3 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT3_STATE9 :: reserved_for_eco0 [31:10] */
#define BCHP_XPT_RAVE_TPIT3_STATE9_reserved_for_eco0_MASK          0xfffffc00
#define BCHP_XPT_RAVE_TPIT3_STATE9_reserved_for_eco0_SHIFT         10

/* XPT_RAVE :: TPIT3_STATE9 :: TPIT_LAST_TICK_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT3_STATE9_TPIT_LAST_TICK_HI_MASK          0x000003ff
#define BCHP_XPT_RAVE_TPIT3_STATE9_TPIT_LAST_TICK_HI_SHIFT         0

/***************************************************************************
 *TPIT4_CTRL1 - TPIT 4 Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_CTRL1 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_reserved_for_eco0_MASK           0xfffffe00
#define BCHP_XPT_RAVE_TPIT4_CTRL1_reserved_for_eco0_SHIFT          9

/* XPT_RAVE :: TPIT4_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK       0x00000100
#define BCHP_XPT_RAVE_TPIT4_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT      8

/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_TIME_TICK_EN_MASK           0x00000080
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_TIME_TICK_EN_SHIFT          7

/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_SPAN_SECTION_EN_MASK        0x00000060
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT       5

/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_PCR_MODE [04:04] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_PCR_MODE_MASK               0x00000010
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_PCR_MODE_SHIFT              4

/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EVENT_IDLE_EN_MASK          0x00000008
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT         3

/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_EMM_TID_EN [02:02] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EMM_TID_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EMM_TID_EN_SHIFT            2

/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_RECORD_IDLE_EN_MASK         0x00000002
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT        1

/* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_FIRST_PACKET_EN_MASK        0x00000001
#define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT       0

/***************************************************************************
 *TPIT4_COR1 - TPIT 4 Corrupt Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_COR1 :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT4_COR1_reserved_for_eco0_MASK            0xff000000
#define BCHP_XPT_RAVE_TPIT4_COR1_reserved_for_eco0_SHIFT           24

/* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_BYTE [23:16] */
#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_BYTE_MASK             0x00ff0000
#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_BYTE_SHIFT            16

/* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_START [15:08] */
#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_START_MASK            0x0000ff00
#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_START_SHIFT           8

/* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_END [07:00] */
#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_END_MASK              0x000000ff
#define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_END_SHIFT             0

/***************************************************************************
 *TPIT4_TID - TPIT TID Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_TID :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco0_MASK             0xff000000
#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco0_SHIFT            24

/* XPT_RAVE :: TPIT4_TID :: ECM_TID_ODD [23:16] */
#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_ODD_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_ODD_SHIFT                  16

/* XPT_RAVE :: TPIT4_TID :: ECM_TID_EVEN [15:08] */
#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_EVEN_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_EVEN_SHIFT                 8

/* XPT_RAVE :: TPIT4_TID :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco1_MASK             0x000000f0
#define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco1_SHIFT            4

/* XPT_RAVE :: TPIT4_TID :: EMM_TID [03:00] */
#define BCHP_XPT_RAVE_TPIT4_TID_EMM_TID_MASK                       0x0000000f
#define BCHP_XPT_RAVE_TPIT4_TID_EMM_TID_SHIFT                      0

/***************************************************************************
 *TPIT4_TID2 - TPIT TID Register 2
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_ODD3 [31:24] */
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD3_MASK                 0xff000000
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD3_SHIFT                24

/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_EVEN3 [23:16] */
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN3_MASK                0x00ff0000
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN3_SHIFT               16

/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_ODD2 [15:08] */
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD2_MASK                 0x0000ff00
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD2_SHIFT                8

/* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_EVEN2 [07:00] */
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN2_MASK                0x000000ff
#define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN2_SHIFT               0

/***************************************************************************
 *TPIT4_STATE0 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE0 :: TPIT_TRACK_STATE0 [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE0_TPIT_TRACK_STATE0_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE0_TPIT_TRACK_STATE0_SHIFT         0

/***************************************************************************
 *TPIT4_STATE1 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE1 :: TPIT_TRACK_STATE1 [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE1_TPIT_TRACK_STATE1_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE1_TPIT_TRACK_STATE1_SHIFT         0

/***************************************************************************
 *TPIT4_STATE2 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE2 :: TPIT_TRACK_STATE2 [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE2_TPIT_TRACK_STATE2_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE2_TPIT_TRACK_STATE2_SHIFT         0

/***************************************************************************
 *TPIT4_STATE2a - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE2a :: TPIT_TRACK_STATE2a [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE2a_TPIT_TRACK_STATE2a_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE2a_TPIT_TRACK_STATE2a_SHIFT       0

/***************************************************************************
 *TPIT4_STATE2b - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE2b :: TPIT_TRACK_STATE2b [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE2b_TPIT_TRACK_STATE2b_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE2b_TPIT_TRACK_STATE2b_SHIFT       0

/***************************************************************************
 *TPIT4_STATE2c - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE2c :: TPIT_TRACK_STATE2c [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE2c_TPIT_TRACK_STATE2c_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE2c_TPIT_TRACK_STATE2c_SHIFT       0

/***************************************************************************
 *TPIT4_STATE2d - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE2d :: TPIT_TRACK_STATE2d [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE2d_TPIT_TRACK_STATE2d_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE2d_TPIT_TRACK_STATE2d_SHIFT       0

/***************************************************************************
 *TPIT4_STATE3 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE3 :: TPIT_TRACK_STATE3 [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE3_TPIT_TRACK_STATE3_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE3_TPIT_TRACK_STATE3_SHIFT         0

/***************************************************************************
 *TPIT4_STATE4 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE4 :: TPIT_CUR_PCR [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE4_TPIT_CUR_PCR_MASK               0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE4_TPIT_CUR_PCR_SHIFT              0

/***************************************************************************
 *TPIT4_STATE5 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE5_TPIT_LAST_PACKET_LO_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE5_TPIT_LAST_PACKET_LO_SHIFT       0

/***************************************************************************
 *TPIT4_STATE6 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE6_TPIT_LAST_EVENT_LO_MASK         0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE6_TPIT_LAST_EVENT_LO_SHIFT        0

/***************************************************************************
 *TPIT4_STATE7 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE7 :: reserved_for_eco0 [31:20] */
#define BCHP_XPT_RAVE_TPIT4_STATE7_reserved_for_eco0_MASK          0xfff00000
#define BCHP_XPT_RAVE_TPIT4_STATE7_reserved_for_eco0_SHIFT         20

/* XPT_RAVE :: TPIT4_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */
#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_EVENT_HI_MASK         0x000ffc00
#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_EVENT_HI_SHIFT        10

/* XPT_RAVE :: TPIT4_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_PACKET_HI_MASK        0x000003ff
#define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_PACKET_HI_SHIFT       0

/***************************************************************************
 *TPIT4_STATE8 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE8 :: TPIT_LAST_TICK_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE8_TPIT_LAST_TICK_LO_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT4_STATE8_TPIT_LAST_TICK_LO_SHIFT         0

/***************************************************************************
 *TPIT4_STATE9 - TPIT 4 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT4_STATE9 :: reserved_for_eco0 [31:10] */
#define BCHP_XPT_RAVE_TPIT4_STATE9_reserved_for_eco0_MASK          0xfffffc00
#define BCHP_XPT_RAVE_TPIT4_STATE9_reserved_for_eco0_SHIFT         10

/* XPT_RAVE :: TPIT4_STATE9 :: TPIT_LAST_TICK_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT4_STATE9_TPIT_LAST_TICK_HI_MASK          0x000003ff
#define BCHP_XPT_RAVE_TPIT4_STATE9_TPIT_LAST_TICK_HI_SHIFT         0

/***************************************************************************
 *TPIT5_CTRL1 - TPIT 5 Control Register 1
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_CTRL1 :: reserved_for_eco0 [31:09] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_reserved_for_eco0_MASK           0xfffffe00
#define BCHP_XPT_RAVE_TPIT5_CTRL1_reserved_for_eco0_SHIFT          9

/* XPT_RAVE :: TPIT5_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK       0x00000100
#define BCHP_XPT_RAVE_TPIT5_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT      8

/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_TIME_TICK_EN_MASK           0x00000080
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_TIME_TICK_EN_SHIFT          7

/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_SPAN_SECTION_EN_MASK        0x00000060
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT       5

/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_PCR_MODE [04:04] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_PCR_MODE_MASK               0x00000010
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_PCR_MODE_SHIFT              4

/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EVENT_IDLE_EN_MASK          0x00000008
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT         3

/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_EMM_TID_EN [02:02] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EMM_TID_EN_MASK             0x00000004
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EMM_TID_EN_SHIFT            2

/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_RECORD_IDLE_EN_MASK         0x00000002
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT        1

/* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_FIRST_PACKET_EN_MASK        0x00000001
#define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT       0

/***************************************************************************
 *TPIT5_COR1 - TPIT 5 Corrupt Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_COR1 :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT5_COR1_reserved_for_eco0_MASK            0xff000000
#define BCHP_XPT_RAVE_TPIT5_COR1_reserved_for_eco0_SHIFT           24

/* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_BYTE [23:16] */
#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_BYTE_MASK             0x00ff0000
#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_BYTE_SHIFT            16

/* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_START [15:08] */
#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_START_MASK            0x0000ff00
#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_START_SHIFT           8

/* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_END [07:00] */
#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_END_MASK              0x000000ff
#define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_END_SHIFT             0

/***************************************************************************
 *TPIT5_TID - TPIT TID Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_TID :: reserved_for_eco0 [31:24] */
#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco0_MASK             0xff000000
#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco0_SHIFT            24

/* XPT_RAVE :: TPIT5_TID :: ECM_TID_ODD [23:16] */
#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_ODD_MASK                   0x00ff0000
#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_ODD_SHIFT                  16

/* XPT_RAVE :: TPIT5_TID :: ECM_TID_EVEN [15:08] */
#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_EVEN_MASK                  0x0000ff00
#define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_EVEN_SHIFT                 8

/* XPT_RAVE :: TPIT5_TID :: reserved_for_eco1 [07:04] */
#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco1_MASK             0x000000f0
#define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco1_SHIFT            4

/* XPT_RAVE :: TPIT5_TID :: EMM_TID [03:00] */
#define BCHP_XPT_RAVE_TPIT5_TID_EMM_TID_MASK                       0x0000000f
#define BCHP_XPT_RAVE_TPIT5_TID_EMM_TID_SHIFT                      0

/***************************************************************************
 *TPIT5_TID2 - TPIT TID Register 2
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_ODD3 [31:24] */
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD3_MASK                 0xff000000
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD3_SHIFT                24

/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_EVEN3 [23:16] */
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN3_MASK                0x00ff0000
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN3_SHIFT               16

/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_ODD2 [15:08] */
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD2_MASK                 0x0000ff00
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD2_SHIFT                8

/* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_EVEN2 [07:00] */
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN2_MASK                0x000000ff
#define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN2_SHIFT               0

/***************************************************************************
 *TPIT5_STATE0 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE0 :: TPIT_TRACK_STATE0 [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE0_TPIT_TRACK_STATE0_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE0_TPIT_TRACK_STATE0_SHIFT         0

/***************************************************************************
 *TPIT5_STATE1 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE1 :: TPIT_TRACK_STATE1 [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE1_TPIT_TRACK_STATE1_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE1_TPIT_TRACK_STATE1_SHIFT         0

/***************************************************************************
 *TPIT5_STATE2 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE2 :: TPIT_TRACK_STATE2 [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE2_TPIT_TRACK_STATE2_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE2_TPIT_TRACK_STATE2_SHIFT         0

/***************************************************************************
 *TPIT5_STATE2a - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE2a :: TPIT_TRACK_STATE2a [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE2a_TPIT_TRACK_STATE2a_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE2a_TPIT_TRACK_STATE2a_SHIFT       0

/***************************************************************************
 *TPIT5_STATE2b - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE2b :: TPIT_TRACK_STATE2b [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE2b_TPIT_TRACK_STATE2b_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE2b_TPIT_TRACK_STATE2b_SHIFT       0

/***************************************************************************
 *TPIT5_STATE2c - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE2c :: TPIT_TRACK_STATE2c [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE2c_TPIT_TRACK_STATE2c_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE2c_TPIT_TRACK_STATE2c_SHIFT       0

/***************************************************************************
 *TPIT5_STATE2d - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE2d :: TPIT_TRACK_STATE2d [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE2d_TPIT_TRACK_STATE2d_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE2d_TPIT_TRACK_STATE2d_SHIFT       0

/***************************************************************************
 *TPIT5_STATE3 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE3 :: TPIT_TRACK_STATE3 [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE3_TPIT_TRACK_STATE3_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE3_TPIT_TRACK_STATE3_SHIFT         0

/***************************************************************************
 *TPIT5_STATE4 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE4 :: TPIT_CUR_PCR [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE4_TPIT_CUR_PCR_MASK               0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE4_TPIT_CUR_PCR_SHIFT              0

/***************************************************************************
 *TPIT5_STATE5 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE5_TPIT_LAST_PACKET_LO_MASK        0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE5_TPIT_LAST_PACKET_LO_SHIFT       0

/***************************************************************************
 *TPIT5_STATE6 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE6_TPIT_LAST_EVENT_LO_MASK         0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE6_TPIT_LAST_EVENT_LO_SHIFT        0

/***************************************************************************
 *TPIT5_STATE7 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE7 :: reserved_for_eco0 [31:20] */
#define BCHP_XPT_RAVE_TPIT5_STATE7_reserved_for_eco0_MASK          0xfff00000
#define BCHP_XPT_RAVE_TPIT5_STATE7_reserved_for_eco0_SHIFT         20

/* XPT_RAVE :: TPIT5_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */
#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_EVENT_HI_MASK         0x000ffc00
#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_EVENT_HI_SHIFT        10

/* XPT_RAVE :: TPIT5_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_PACKET_HI_MASK        0x000003ff
#define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_PACKET_HI_SHIFT       0

/***************************************************************************
 *TPIT5_STATE8 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE8 :: TPIT_LAST_TICK_LO [31:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE8_TPIT_LAST_TICK_LO_MASK          0xffffffff
#define BCHP_XPT_RAVE_TPIT5_STATE8_TPIT_LAST_TICK_LO_SHIFT         0

/***************************************************************************
 *TPIT5_STATE9 - TPIT 5 State Register
 ***************************************************************************/
/* XPT_RAVE :: TPIT5_STATE9 :: reserved_for_eco0 [31:10] */
#define BCHP_XPT_RAVE_TPIT5_STATE9_reserved_for_eco0_MASK          0xfffffc00
#define BCHP_XPT_RAVE_TPIT5_STATE9_reserved_for_eco0_SHIFT         10

/* XPT_RAVE :: TPIT5_STATE9 :: TPIT_LAST_TICK_HI [09:00] */
#define BCHP_XPT_RAVE_TPIT5_STATE9_TPIT_LAST_TICK_HI_MASK          0x000003ff
#define BCHP_XPT_RAVE_TPIT5_STATE9_TPIT_LAST_TICK_HI_SHIFT         0

/***************************************************************************
 *TPIT_STATE_CONTEXT0 - TPIT State Register for Context 0
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT0 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT0 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT1 - TPIT State Register for Context 1
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT1 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT1 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT2 - TPIT State Register for Context 2
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT2 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT2 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT3 - TPIT State Register for Context 3
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT3 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT3 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT4 - TPIT State Register for Context 4
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT4 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT4 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT5 - TPIT State Register for Context 5
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT5 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT5 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT6 - TPIT State Register for Context 6
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT6 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT6 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT7 - TPIT State Register for Context 7
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT7 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT7 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT8 - TPIT State Register for Context 8
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT8 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT8 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT9 - TPIT State Register for Context 9
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT9 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_reserved0_MASK           0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_reserved0_SHIFT          8

/* XPT_RAVE :: TPIT_STATE_CONTEXT9 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT10 - TPIT State Register for Context 10
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT10 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT10 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT11 - TPIT State Register for Context 11
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT11 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT11 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT12 - TPIT State Register for Context 12
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT12 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT12 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT13 - TPIT State Register for Context 13
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT13 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT13 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT14 - TPIT State Register for Context 14
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT14 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT14 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT15 - TPIT State Register for Context 15
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT15 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT15 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT16 - TPIT State Register for Context 16
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT16 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT16 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT17 - TPIT State Register for Context 17
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT17 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT17 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT18 - TPIT State Register for Context 18
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT18 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT18 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT19 - TPIT State Register for Context 19
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT19 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT19 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT20 - TPIT State Register for Context 20
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT20 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT20 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT21 - TPIT State Register for Context 21
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT21 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT21 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT22 - TPIT State Register for Context 22
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT22 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT22 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

/***************************************************************************
 *TPIT_STATE_CONTEXT23 - TPIT State Register for Context 23
 ***************************************************************************/
/* XPT_RAVE :: TPIT_STATE_CONTEXT23 :: reserved0 [31:08] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_reserved0_MASK          0xffffff00
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_reserved0_SHIFT         8

/* XPT_RAVE :: TPIT_STATE_CONTEXT23 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff
#define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0

#endif /* #ifndef BCHP_XPT_RAVE_H__ */

/* End of File */
