/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 **********************************************************************
 * This file is part of the crystalhd device driver.
 *
 * This driver is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2 of the License.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
 **********************************************************************
 *
 * $brcm_Workfile: bchp_l1_intr.h $
 * $brcm_Revision: Hydra_Software_Devel/1 $
 * $brcm_Date: 7/17/09 8:10p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jul 17 19:42:52 2009
 *                 MD5 Checksum         2914699efc3fb3edefca5cb4f4f38b34
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.h $
 * 
 * Hydra_Software_Devel/1   7/17/09 8:10p albertl
 * PR56880: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_L1_INTR_H__
#define BCHP_L1_INTR_H__

/***************************************************************************
 *L1_INTR - TGT L1 Interrupt Controller Registers (feeds into L2 above)
 ***************************************************************************/
#define BCHP_L1_INTR_INTR_W0_STATUS              0x00500740 /* Interrupt Status Register */
#define BCHP_L1_INTR_INTR_W1_STATUS              0x00500744 /* Interrupt Status Register */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS         0x00500748 /* Interrupt Mask Status Register */
#define BCHP_L1_INTR_INTR_W1_MASK_STATUS         0x0050074c /* Interrupt Mask Status Register */
#define BCHP_L1_INTR_INTR_W0_MASK_SET            0x00500750 /* Interrupt Mask Set Register */
#define BCHP_L1_INTR_INTR_W1_MASK_SET            0x00500754 /* Interrupt Mask Set Register */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR          0x00500758 /* Interrupt Mask Clear Register */
#define BCHP_L1_INTR_INTR_W1_MASK_CLEAR          0x0050075c /* Interrupt Mask Clear Register */

/***************************************************************************
 *INTR_W0_STATUS - Interrupt Status Register
 ***************************************************************************/
/* L1_INTR :: INTR_W0_STATUS :: reserved0 [31:16] */
#define BCHP_L1_INTR_INTR_W0_STATUS_reserved0_MASK                 0xffff0000
#define BCHP_L1_INTR_INTR_W0_STATUS_reserved0_SHIFT                16

/* L1_INTR :: INTR_W0_STATUS :: BVN_INTR [15:15] */
#define BCHP_L1_INTR_INTR_W0_STATUS_BVN_INTR_MASK                  0x00008000
#define BCHP_L1_INTR_INTR_W0_STATUS_BVN_INTR_SHIFT                 15

/* L1_INTR :: INTR_W0_STATUS :: BLINK_INTR [14:14] */
#define BCHP_L1_INTR_INTR_W0_STATUS_BLINK_INTR_MASK                0x00004000
#define BCHP_L1_INTR_INTR_W0_STATUS_BLINK_INTR_SHIFT               14

/* L1_INTR :: INTR_W0_STATUS :: SECURE_INTR [13:13] */
#define BCHP_L1_INTR_INTR_W0_STATUS_SECURE_INTR_MASK               0x00002000
#define BCHP_L1_INTR_INTR_W0_STATUS_SECURE_INTR_SHIFT              13

/* L1_INTR :: INTR_W0_STATUS :: ARB_RTS_INTR [12:12] */
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_RTS_INTR_MASK              0x00001000
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_RTS_INTR_SHIFT             12

/* L1_INTR :: INTR_W0_STATUS :: ARB_CRIT_INTR [11:11] */
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_CRIT_INTR_MASK             0x00000800
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_CRIT_INTR_SHIFT            11

/* L1_INTR :: INTR_W0_STATUS :: ARB_ARCH_INTR [10:10] */
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_ARCH_INTR_MASK             0x00000400
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_ARCH_INTR_SHIFT            10

/* L1_INTR :: INTR_W0_STATUS :: ARB_MEM_INTR [09:09] */
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_MEM_INTR_MASK              0x00000200
#define BCHP_L1_INTR_INTR_W0_STATUS_ARB_MEM_INTR_SHIFT             9

/* L1_INTR :: INTR_W0_STATUS :: UPG_MAIN_INTR [08:08] */
#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_MAIN_INTR_MASK             0x00000100
#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_MAIN_INTR_SHIFT            8

/* L1_INTR :: INTR_W0_STATUS :: UPG_TMR_INTR [07:07] */
#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_TMR_INTR_MASK              0x00000080
#define BCHP_L1_INTR_INTR_W0_STATUS_UPG_TMR_INTR_SHIFT             7

/* L1_INTR :: INTR_W0_STATUS :: SUN_INTR [06:06] */
#define BCHP_L1_INTR_INTR_W0_STATUS_SUN_INTR_MASK                  0x00000040
#define BCHP_L1_INTR_INTR_W0_STATUS_SUN_INTR_SHIFT                 6

/* L1_INTR :: INTR_W0_STATUS :: AVD_INTR [05:05] */
#define BCHP_L1_INTR_INTR_W0_STATUS_AVD_INTR_MASK                  0x00000020
#define BCHP_L1_INTR_INTR_W0_STATUS_AVD_INTR_SHIFT                 5

/* L1_INTR :: INTR_W0_STATUS :: XPT_STATUS_INTR [04:04] */
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_STATUS_INTR_MASK           0x00000010
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_STATUS_INTR_SHIFT          4

/* L1_INTR :: INTR_W0_STATUS :: XPT_PCR_INTR [03:03] */
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_PCR_INTR_MASK              0x00000008
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_PCR_INTR_SHIFT             3

/* L1_INTR :: INTR_W0_STATUS :: XPT_FE_INTR [02:02] */
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_FE_INTR_MASK               0x00000004
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_FE_INTR_SHIFT              2

/* L1_INTR :: INTR_W0_STATUS :: XPT_RAV_INTR [01:01] */
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_RAV_INTR_MASK              0x00000002
#define BCHP_L1_INTR_INTR_W0_STATUS_XPT_RAV_INTR_SHIFT             1

/* L1_INTR :: INTR_W0_STATUS :: WRAP_MISC_INTR [00:00] */
#define BCHP_L1_INTR_INTR_W0_STATUS_WRAP_MISC_INTR_MASK            0x00000001
#define BCHP_L1_INTR_INTR_W0_STATUS_WRAP_MISC_INTR_SHIFT           0

/***************************************************************************
 *INTR_W1_STATUS - Interrupt Status Register
 ***************************************************************************/
/* L1_INTR :: INTR_W1_STATUS :: reserved0 [31:00] */
#define BCHP_L1_INTR_INTR_W1_STATUS_reserved0_MASK                 0xffffffff
#define BCHP_L1_INTR_INTR_W1_STATUS_reserved0_SHIFT                0

/***************************************************************************
 *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* L1_INTR :: INTR_W0_MASK_STATUS :: reserved0 [31:16] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_reserved0_MASK            0xffff0000
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_reserved0_SHIFT           16

/* L1_INTR :: INTR_W0_MASK_STATUS :: BVN_MASK [15:15] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BVN_MASK_MASK             0x00008000
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BVN_MASK_SHIFT            15

/* L1_INTR :: INTR_W0_MASK_STATUS :: BLINK_MASK [14:14] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BLINK_MASK_MASK           0x00004000
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BLINK_MASK_SHIFT          14

/* L1_INTR :: INTR_W0_MASK_STATUS :: SECURE_MASK [13:13] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SECURE_MASK_MASK          0x00002000
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SECURE_MASK_SHIFT         13

/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_RTS_MASK [12:12] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_RTS_MASK_MASK         0x00001000
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_RTS_MASK_SHIFT        12

/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_CRIT_MASK [11:11] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_CRIT_MASK_MASK        0x00000800
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_CRIT_MASK_SHIFT       11

/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_ARCH_MASK [10:10] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_ARCH_MASK_MASK        0x00000400
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_ARCH_MASK_SHIFT       10

/* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_MEM_MASK [09:09] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_MEM_MASK_MASK         0x00000200
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_MEM_MASK_SHIFT        9

/* L1_INTR :: INTR_W0_MASK_STATUS :: UPG_MAIN_MASK [08:08] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_MAIN_MASK_MASK        0x00000100
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_MAIN_MASK_SHIFT       8

/* L1_INTR :: INTR_W0_MASK_STATUS :: UPG_TMR_MASK [07:07] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_TMR_MASK_MASK         0x00000080
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_TMR_MASK_SHIFT        7

/* L1_INTR :: INTR_W0_MASK_STATUS :: SUN_MASK [06:06] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SUN_MASK_MASK             0x00000040
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SUN_MASK_SHIFT            6

/* L1_INTR :: INTR_W0_MASK_STATUS :: AVD_MASK [05:05] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_AVD_MASK_MASK             0x00000020
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_AVD_MASK_SHIFT            5

/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_STATUS_MASK [04:04] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_STATUS_MASK_MASK      0x00000010
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_STATUS_MASK_SHIFT     4

/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_PCR_MASK [03:03] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_PCR_MASK_MASK         0x00000008
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_PCR_MASK_SHIFT        3

/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_FE_MASK [02:02] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_FE_MASK_MASK          0x00000004
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_FE_MASK_SHIFT         2

/* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_RAV_MASK [01:01] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_RAV_MASK_MASK         0x00000002
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_RAV_MASK_SHIFT        1

/* L1_INTR :: INTR_W0_MASK_STATUS :: WRAP_MISC_MASK [00:00] */
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_WRAP_MISC_MASK_MASK       0x00000001
#define BCHP_L1_INTR_INTR_W0_MASK_STATUS_WRAP_MISC_MASK_SHIFT      0

/***************************************************************************
 *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* L1_INTR :: INTR_W1_MASK_STATUS :: reserved0 [31:00] */
#define BCHP_L1_INTR_INTR_W1_MASK_STATUS_reserved0_MASK            0xffffffff
#define BCHP_L1_INTR_INTR_W1_MASK_STATUS_reserved0_SHIFT           0

/***************************************************************************
 *INTR_W0_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* L1_INTR :: INTR_W0_MASK_SET :: reserved0 [31:16] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_reserved0_MASK               0xffff0000
#define BCHP_L1_INTR_INTR_W0_MASK_SET_reserved0_SHIFT              16

/* L1_INTR :: INTR_W0_MASK_SET :: BVN_MASK [15:15] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_BVN_MASK_MASK                0x00008000
#define BCHP_L1_INTR_INTR_W0_MASK_SET_BVN_MASK_SHIFT               15

/* L1_INTR :: INTR_W0_MASK_SET :: BLINK_MASK [14:14] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_BLINK_MASK_MASK              0x00004000
#define BCHP_L1_INTR_INTR_W0_MASK_SET_BLINK_MASK_SHIFT             14

/* L1_INTR :: INTR_W0_MASK_SET :: SECURE_MASK [13:13] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_SECURE_MASK_MASK             0x00002000
#define BCHP_L1_INTR_INTR_W0_MASK_SET_SECURE_MASK_SHIFT            13

/* L1_INTR :: INTR_W0_MASK_SET :: ARB_RTS_MASK [12:12] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_RTS_MASK_MASK            0x00001000
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_RTS_MASK_SHIFT           12

/* L1_INTR :: INTR_W0_MASK_SET :: ARB_CRIT_MASK [11:11] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_CRIT_MASK_MASK           0x00000800
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_CRIT_MASK_SHIFT          11

/* L1_INTR :: INTR_W0_MASK_SET :: ARB_ARCH_MASK [10:10] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_ARCH_MASK_MASK           0x00000400
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_ARCH_MASK_SHIFT          10

/* L1_INTR :: INTR_W0_MASK_SET :: ARB_MEM_MASK [09:09] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_MEM_MASK_MASK            0x00000200
#define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_MEM_MASK_SHIFT           9

/* L1_INTR :: INTR_W0_MASK_SET :: UPG_MAIN_MASK [08:08] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_MAIN_MASK_MASK           0x00000100
#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_MAIN_MASK_SHIFT          8

/* L1_INTR :: INTR_W0_MASK_SET :: UPG_TMR_MASK [07:07] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_TMR_MASK_MASK            0x00000080
#define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_TMR_MASK_SHIFT           7

/* L1_INTR :: INTR_W0_MASK_SET :: SUN_MASK [06:06] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_SUN_MASK_MASK                0x00000040
#define BCHP_L1_INTR_INTR_W0_MASK_SET_SUN_MASK_SHIFT               6

/* L1_INTR :: INTR_W0_MASK_SET :: AVD_MASK [05:05] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_AVD_MASK_MASK                0x00000020
#define BCHP_L1_INTR_INTR_W0_MASK_SET_AVD_MASK_SHIFT               5

/* L1_INTR :: INTR_W0_MASK_SET :: XPT_STATUS_MASK [04:04] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_STATUS_MASK_MASK         0x00000010
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_STATUS_MASK_SHIFT        4

/* L1_INTR :: INTR_W0_MASK_SET :: XPT_PCR_MASK [03:03] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_PCR_MASK_MASK            0x00000008
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_PCR_MASK_SHIFT           3

/* L1_INTR :: INTR_W0_MASK_SET :: XPT_FE_MASK [02:02] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_FE_MASK_MASK             0x00000004
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_FE_MASK_SHIFT            2

/* L1_INTR :: INTR_W0_MASK_SET :: XPT_RAV_MASK [01:01] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_RAV_MASK_MASK            0x00000002
#define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_RAV_MASK_SHIFT           1

/* L1_INTR :: INTR_W0_MASK_SET :: WRAP_MISC_MASK [00:00] */
#define BCHP_L1_INTR_INTR_W0_MASK_SET_WRAP_MISC_MASK_MASK          0x00000001
#define BCHP_L1_INTR_INTR_W0_MASK_SET_WRAP_MISC_MASK_SHIFT         0

/***************************************************************************
 *INTR_W1_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* L1_INTR :: INTR_W1_MASK_SET :: reserved0 [31:00] */
#define BCHP_L1_INTR_INTR_W1_MASK_SET_reserved0_MASK               0xffffffff
#define BCHP_L1_INTR_INTR_W1_MASK_SET_reserved0_SHIFT              0

/***************************************************************************
 *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* L1_INTR :: INTR_W0_MASK_CLEAR :: reserved0 [31:16] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_reserved0_MASK             0xffff0000
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_reserved0_SHIFT            16

/* L1_INTR :: INTR_W0_MASK_CLEAR :: BVN_MASK [15:15] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BVN_MASK_MASK              0x00008000
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BVN_MASK_SHIFT             15

/* L1_INTR :: INTR_W0_MASK_CLEAR :: BLINK_MASK [14:14] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BLINK_MASK_MASK            0x00004000
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BLINK_MASK_SHIFT           14

/* L1_INTR :: INTR_W0_MASK_CLEAR :: SECURE_MASK [13:13] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SECURE_MASK_MASK           0x00002000
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SECURE_MASK_SHIFT          13

/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_RTS_MASK [12:12] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_RTS_MASK_MASK          0x00001000
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_RTS_MASK_SHIFT         12

/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_CRIT_MASK [11:11] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_CRIT_MASK_MASK         0x00000800
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_CRIT_MASK_SHIFT        11

/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_ARCH_MASK [10:10] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_ARCH_MASK_MASK         0x00000400
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_ARCH_MASK_SHIFT        10

/* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_MEM_MASK [09:09] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_MEM_MASK_MASK          0x00000200
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_MEM_MASK_SHIFT         9

/* L1_INTR :: INTR_W0_MASK_CLEAR :: UPG_MAIN_MASK [08:08] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_MAIN_MASK_MASK         0x00000100
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_MAIN_MASK_SHIFT        8

/* L1_INTR :: INTR_W0_MASK_CLEAR :: UPG_TMR_MASK [07:07] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_TMR_MASK_MASK          0x00000080
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_TMR_MASK_SHIFT         7

/* L1_INTR :: INTR_W0_MASK_CLEAR :: SUN_MASK [06:06] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SUN_MASK_MASK              0x00000040
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SUN_MASK_SHIFT             6

/* L1_INTR :: INTR_W0_MASK_CLEAR :: AVD_MASK [05:05] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_AVD_MASK_MASK              0x00000020
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_AVD_MASK_SHIFT             5

/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_STATUS_MASK [04:04] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_STATUS_MASK_MASK       0x00000010
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_STATUS_MASK_SHIFT      4

/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_PCR_MASK [03:03] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_PCR_MASK_MASK          0x00000008
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_PCR_MASK_SHIFT         3

/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_FE_MASK [02:02] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_FE_MASK_MASK           0x00000004
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_FE_MASK_SHIFT          2

/* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_RAV_MASK [01:01] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_RAV_MASK_MASK          0x00000002
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_RAV_MASK_SHIFT         1

/* L1_INTR :: INTR_W0_MASK_CLEAR :: WRAP_MISC_MASK [00:00] */
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_WRAP_MISC_MASK_MASK        0x00000001
#define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_WRAP_MISC_MASK_SHIFT       0

/***************************************************************************
 *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* L1_INTR :: INTR_W1_MASK_CLEAR :: reserved0 [31:00] */
#define BCHP_L1_INTR_INTR_W1_MASK_CLEAR_reserved0_MASK             0xffffffff
#define BCHP_L1_INTR_INTR_W1_MASK_CLEAR_reserved0_SHIFT            0

#endif /* #ifndef BCHP_L1_INTR_H__ */

/* End of File */
